 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00124 re v. *f revised august 07, 2017 s25fl256l/S25FL128L 256mbit (32mbyte)/128mbit (16mbyte), 3.0 v fl-l flash memory general description the cypress fl-l family devices are flas h non-volatile memory products using: ? floating gate technology ? 65 nm process lithography the fl-l family connects to a host system via a serial peripheral inte rface (spi). traditional spi single bit serial input and output (single i/o or sio) is supported as well as optional two bit (dual i/o or dio) and four bit wide quad i/o (qio) and quad periph eral interface (qpi) commands. in addition, ther e are double data rate (ddr) read command s for qio and qpi that transfer address and read data on both edges of the clock. the architecture features a page programming buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4kb sector, 32kb half block, 64kb block, or entire chip erase. by using fl-l family devices at the higher clock rates supported, with quad commands, the instruction read transfer rate can ma tch or exceed traditional parallel interface, asynchronous, no r flash memories, while reducing signal count dramatically. the fl-l family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. provides an ideal storage solution for syst ems with limited space, signal connections, and power. these memories offer flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly (xip), and storing re-programmable data. features ? serial peripheral interf ace (spi) with multi-i/o ? clock polarity and phase modes 0 and 3 ? double data rate (ddr) option ? quad peripheral interface (qpi) option ? extended addressing: 24- or 32-bit address options ? serial command subset and footprint compatible with s25fl-a, s25fl1-k, s25fl-p, s25fl-s and s25fs-s spi families ? multi i/o command subset and footprint compatible with s25fl-p, s25fl-s and s25fs-s spi families ? read ? commands: normal, fast, dual i/o, quad i/o, dualo, quado, ddr quad i/o. ? modes: burst wrap, continuous (xip), qpi ? serial flash discoverable parameters (sfdp) for configuration information. ? program architecture ? 256 bytes page programming buffer3.0 v fl-l flash memory ? program suspend and resume ? erase architecture ? uniform 4kb sector erase ? uniform 32kb half block erase ? uniform 64kb block erase ? chip erase ? erase suspend and resume ? 100,000 program/eras e cycles, minimum ? 20 year data retention, minimum ? security features ? status and configuration register protection ? four security regions of 256 bytes each outside the main flash array ? legacy block protection: block range ? individual and region protection ? individual block lock: volati le individual sector/block ? pointer region: non-volatile sector/block range ? power supply lock-down, password, or permanent protection of security regions 2 and 3 and pointer region ? technology ? 65 nm floating gate technology ? single supply voltage with cmos i/o ? 2.7 v to 3.6 v ? temperature range / grade ? industrial (?40c to +85c) ? industrial plus (?40c to +105c) ? automotive, aec-q100 grade 3 (?40c to +85c) ? automotive, aec-q100 grade 2 (?40c to +105c) ? automotive, aec-q100 grade 1 (?40c to +125c) ? packages (all pb-free) ? 8-pin soic 208 mil (soc008) ? S25FL128L only ?wson 5 ? 6 mm (wnd008) ? S25FL128L only ?wson 6 ? 8 mm (wng008) ? s25fl256l only ? 16-pin soic 300 mil (so3016) ? bga-24 6 ? 8 mm ?5 ? 5 ball (fab024) footprint ? 4 ? 6 ball (fac024) footprin t
document number: 002-00124 rev. *f page 2 of 158 s25fl256l/S25FL128L performance summary maximum read rates sdr command clock rate (mhz) mbps read 50 6.25 fast read 133 16.5 dual read 133 33 quad read 133 66 maximum read rates ddr command clock rate (mhz) mbps ddr quad read 66 66 typical program and erase rates operation kbytes/s page programming 854 4 kbytes sector erase 80 32 kbytes half block erase 168 64 kbytes block erase 237 typical current consumption, ? 40c to +85c operation typical current unit fast read 5mhz 10 ma fast read 10 mhz 10 ma fast read 20 mhz 10 ma fast read 50 mhz 15 ma fast read 108 mhz 25 ma fast read 133 mhz 30 ma quad i/o / qpi read 108 mhz 25 ma quad i/o / qpi read 133 mhz 30 ma quad i/o / qpi ddr read 33mhz 15 ma quad i/o / qpi ddr read 66mhz 30 ma program 40 ma erase 40 ma standby spi 20 a standby qpi 60 a deep power down 2a document number: 002-00124 rev. *f page 3 of 158 s25fl256l/S25FL128L contents 1. product overview ........................................................ 4 1.1 migration notes.............................................................. 4 2. connection diagrams .................................................. 5 2.1 soic 16-lead ................................................................ 5 2.2 8 connector packages................................................... 5 2.3 bga ball footprint ......................................................... 6 2.4 special handling instructions for fbga packages........ 7 3. signal descriptions ..................................................... 8 3.1 input/output summary................................................... 8 3.2 multiple input / output (mio).. ........... ............ ........... ...... 9 3.3 serial clock (sck) ......................................................... 9 3.4 chip select (cs#) .......................................................... 9 3.5 serial input (si) / io0 ..................................................... 9 3.6 serial output (so) / io1................................................. 9 3.7 write protect (wp#) / io2 .............................................. 9 3.8 io3 / reset# ....... .............. ............ ........... ........... ....... 10 3.9 reset# ........... .............. .............. .............. ........... ....... 10 3.10 voltage supply (v cc )................................................... 10 3.11 supply and signal ground (v ss ) ................................. 10 3.12 not connected (nc) .................................................... 10 3.13 reserved for future use (rfu )................................... 10 3.14 do not use (dnu) ................. .............. .............. .......... 11 4. block diagrams .......................................................... 12 4.1 system block diagrams............................................... 12 5. signal protocols ......................................................... 15 5.1 spi clock modes ......................................................... 15 5.2 command protocol ...................................................... 16 5.3 interface states............................................................ 21 5.4 data protection ............................................................ 24 6. address space maps ................................................. 26 6.1 overview ...................................................................... 26 6.2 flash memory array..................................................... 26 6.3 id address space ........................................................ 27 6.4 jedec jesd216 serial flash discoverable parameters (sfdp) space .................... 27 6.5 security regions address space ................................ 27 6.6 registers...................................................................... 28 7. data protection .......................................................... 45 7.1 security regions.......................................................... 45 7.2 deep power down ....................................................... 45 7.3 write enable commands ............................................. 46 7.4 write protect signal ..................................................... 47 7.5 status register protect (srp1, srp0)........................ 47 7.6 array protection ........................................................... 48 7.7 individual and region protection ................................. 55 8. commands ................................................................. 60 8.1 command set summary.............................................. 60 8.2 identification commands ............................................. 66 8.3 register access commands........................................ 69 8.4 read memory array command s ................................. 82 8.5 program flash array commands ................................ 91 8.6 erase flash array commands...................................... 93 8.7 security regions array commands............................ 100 8.8 individual block lock command s ............................... 102 8.9 pointer region command.......... .............. .............. ..... 106 8.10 individual and region protection (irp) commands ......... .............. .............. .............. ..... 107 8.11 reset commands ....................................................... 112 8.12 deep power down commands.. .............. .............. ..... 113 9. data integrity ............................................................. 116 9.1 erase endurance ........................................................ 116 9.2 data retention ............................................................ 116 10. software interface reference .................................. 117 10.1 jedec jesd216b serial flash discoverable paramete rs............................................ 117 10.2 device id address map .............................................. 126 10.3 initial delivery state ........... ......................................... 126 11. electrical specifications ........................................... 127 11.1 absolute maximum ratings ........................................ 127 11.2 latchup characteristics .......... ............ ........... ............. 127 11.3 thermal resistance ................ .................................... 127 11.4 operating ranges....................................................... 128 11.5 power-up and power-down ...... ................................. 129 11.6 dc characteristics ................ ...................................... 131 12. timing specifications ............................................... 134 12.1 key to switching waveforms ...................................... 134 12.2 ac test conditions ............... ...................................... 134 12.3 reset .......................................................................... 135 12.4 sdr ac characteristics........ ...................................... 138 12.5 ddr ac characteristics ......... .................................... 141 12.6 embedded algorithm performa nce tables ................. 143 13. ordering information ................................................ 144 13.1 ordering part number................................................. 144 14. physical diagrams .................................................... 147 14.1 soic 16-lead, 300-mil body width (so3016) ........... 147 14.2 soic 8-lead, 208 mil body width (soc008)............. 148 14.3 wson 8-contact 5 x 6 mm leadless (wnd008) ....... 149 14.4 wson 8-contact 6 x 8 mm leadless (wng008)....... 150 14.5 ball grid array 24-ball 6 x 8 mm (fab024)................. 151 14.6 ball grid array 24-ball 6 x 8 mm (fac024) ................ 152 15. other resources ....................................................... 153 15.1 glossary...................................................................... 153 15.2 link to cypress flash roadm ap................................. 154 15.3 link to software .......................................................... 154 15.4 link to application notes ...... ...................................... 154 13. document history ..................................................... 155 sales, solutions, and legal information ......................... 157 worldwide sales and design supp ort ............ .............. 157 products ....................................................................... 157 psoc? solutions ......................................................... 157 cypress developer community .................................... 157 technical support ................. ....................................... 157 document number: 002-00124 rev. *f page 4 of 158 s25fl256l/S25FL128L 1. product overview 1.1 migration notes 1.1.1 features comparison the fl-l family is command subset and footprint compat ible with prior generation fl-s, fl1-k and fl-p families. note: 1. refer to individual datasheets for further details. table 1. cypress spi families comparison parameter fl-l fl-s fl1-k fl-p technology node 65nm 65nm 90nm 90nm architecture floating gate mirrorbit ? eclipse? floating gate mirrorbit ? release date in production in production in production in production density 256mb 128mb - 1gb 4mb - 64mb 32mb - 256mb bus width x1, x2, x4 x1, x2, x4 x1, x2, x4 x1, x2, x4 supply voltage 2.7 v - 3.6 v 2.7 v - 3.6 v / 1.65 v - 3.6 v v io 2.7 v - 3.6 v 2.7 v - 3.6 v normal read speed 6mb/s (50mhz) 6mb/s (50mhz) 6mb/s (50mhz) 5mb/s (40mhz) fast read speed 16.5mb/s (133mhz) 17mb/s (133mhz) 13mb/s (108mhz) 13mb/s (104mhz) dual read speed 33mb/s (133mhz) 26mb/s (104mhz) 26mb/s (108mhz) 20mb/s (80mhz) quad read speed 66mb/s (133mhz) 52mb/s (104mhz) 52mb/s (108mhz) 40mb/s (80mhz) quad read speed (ddr) 66mb/s (66mhz) 80mb/s (80mhz) ? ? program buffer size 256b 256b / 512b 256b 256b erase sector/block size 4kb / 32kb / 64kb 64kb / 256kb 4kb / 64kb 64kb / 256kb parameter sector size - 4kb (option) ? 4kb sector / block erase rate (typ.) 80 kb/s (4kb) 168 kb/s (32kb 237kb/s (64kb) 500 kb/s 136 kb/s (4kb) 437 kb/s (64kb) 130 kb/s page programming rate (typ.) 854kb/s (256b) 1.2 mb/s (256b) 1.5 mb/s (512b) 365 kb/s 170 kb/s security region / otp 1024b 1024b 768b (3 ? 256b) 506b individual and region protection or advanced sector protection yes yes no no erase suspend/resume yes yes yes no program suspend/resume yes yes yes no operating temperature ?40c to +85c ?40c to +105c ?40c to +125c ?40c to +85c ?40c to +105c ?40c to +85c ?40c to +85c ?40c to +105c document number: 002-00124 rev. *f page 5 of 158 s25fl256l/S25FL128L 2. connection diagrams 2.1 soic 16-lead figure 1. 16-lead soic package (so3016), top view note: 1. the reset# and io3 / reset# inputs have an internal pull-up an d may be left unconnected in the system if quad mode, mode and hardware reset are not in use. 2.2 8 connector packages figure 2. 8-pin plastic sm all outline package (soic8) soic ? 16 nc io3 ? / ? reset# sck si ? / ? io0 1 2 3 1 413 14 15 16 cs# so ? / ? io1 wp# ? / ? io2 vss 5 6 7 8 vcc reset# 9 10 11 12 nc rfu dnu rfu dnu dnu soic cs# so ? / ? io1 wp# ? / ? io2 vss vcc io3 ? / ? reset# sck si ? / ? io0 1 2 3 1 45 6 7 8 document number: 002-00124 rev. *f page 6 of 158 s25fl256l/S25FL128L figure 3. 8-connector package (wson 6x8) (wson 5x6), top view note: 1. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. 2.3 bga ball footprint figure 4. 24-ball bga, 5x5 ba ll footprint (fab024), top view notes: 1. signal connections are in the same relati ve positions as fac024 bga, allowing a si ngle pcb footprint to use either package. 2. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. wson cs# so ? / ? io1 wp# ? / ? io2 vss vcc io3 ? / ? reset# sck si ? / ? io0 2 3 1 4 5 6 7 8 12 345 a a b c d c e nc nc nc nc nc nc nc nc nc nc reset# rfu dnu dnu dnu sck vss vcc cs# rfu wp#/io2 so/io1 si/io0 io3/reset# document number: 002-00124 rev. *f page 7 of 158 s25fl256l/S25FL128L figure 5. 24-ball bga, 4x6 ba ll footprint (fac024), top view note: 1. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. 2.4 special handling instru ctions for fbga packages flash memory devices in bga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. 12 34 a a b c d c e nc nc nc nc nc reset# rfu dnu dnu dnu sck vss vcc cs# rfu wp#/io2 so/io1 si/io0 io3/reset# f nc nc nc nc nc document number: 002-00124 rev. *f page 8 of 158 s25fl256l/S25FL128L 3. signal descriptions serial peripheral interface with mu ltiple input / output (spi-mio) many memory devices connect to their host system with separate pa rallel control, address, and data signals that require a large number of signal connections and larger package size. the large number of connections increase power consumption due to so many signals switching and the la rger package increases cost. the fl-l family reduces the number of signals for connection to the host system by serially transferri ng all control, address, and data information over 6 signals. this redu ces the cost of the memory package, reduces signal switchin g power, and either reduce s the host connection count or frees host con nectors for use in providing other features. the fl-l family uses the industry standard single bit spi and al so supports optional extension commands for two bit (dual) and four bit (quad) wide serial transfers. this multiple wi dth interface is called spi multi-i/o or spi-mio. 3.1 input/output summary notes 1. inputs with internal pull-ups or pull-downs drive less than 2 ? a. only during power-up is the current larger at 150 ? a for 4 ? s. resistance of pull-ups or pull-down resistors with the typical process at vcc = 3.3 v at ? 40 c is ~4.5 m ? and at 90 c is ~6.6 m ? . table 2. signal list signal name type description reset# input hardware reset: low = device resets and returns to standby stat e, ready to receive a command. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used. sck input serial clock. cs# input chip select. si / io0 i/o serial input for single bit data commands or io0 for dual or quad commands. so / io1 i/o serial output for single bit data commands. io1 for dual or quad commands. wp# / io2 i/o write protect when not in quad mode (cr1v[1] = 0 and sr1nv[7] = 1). io2 when in quad mode (cr1v[1] = 1). the signal has an internal pull-up resistor and may be le ft unconnected in the host system if not used for quad commands or write protection. if write protection is enabled by sr1nv[7] = 1 and cr1v[1] = 0, the host system is required to drive wp# high or low during a wrr or wrar command. io3 / reset# i/o io3 in quad-i/o mode, when configuration register 1 quad bit, cr1v[1] =1, or in qpi mode, when configuration register 2 qpi bit, cr2v[3] =1 and cs# is low. reset# when enabled by cr2v[7]=1 and not in quad-i/o mode, cr1v[1] = 0, or when enabled in quad mode, cr1v[1] = 1 and cs# is high. the signal has an internal pull-up resistor and may be le ft unconnected in the host system if not used for quad commands or reset#. v cc supply power supply. v ss supply ground. nc unused not connected. no device internal signal is connected to the pack age connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v cc . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. dnu reserved do not use. a device internal signal may be connected to t he package connector. the c onnection may be used by cypress for test or other purposes and is not intended fo r connection to any host sy stem signal. any dnu signal related function will be inacti ve when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections fo r pcb signal routing channels. do not connect any host syste m signal to this connection. document number: 002-00124 rev. *f page 9 of 158 s25fl256l/S25FL128L 3.2 multiple input / output (mio) traditional spi single bit wide commands (single or sio) send info rmation from the host to the me mory only on the serial input (si) signal. data may be sent back to the host serially on the serial output (so) signal. dual or quad input / output (i/o) commands s end instructions to the memory only on the si/io0 signal. address or data is sent f rom the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. data is returned to t he host similarly as bit pairs on io0 and io1 or four bi t (nibble) groups on io 0, io1, io2, and io3. qpi mode transfers all instructions, addresses, and data from the host to the memory as four bit (nibble) groups on io0, io1, i o2, and io3. data is returned to the host similarly as four bit (nibble) groups on io0, io1, io2, and io3. 3.3 serial clock (sck) this input signal provides the synchronization reference for the spi interface. instructions, add resses, or data input are latc hed on the rising edge of the sck signal. data output cha nges after the falling edge of sck, in sdr commands. 3.4 chip select (cs#) the chip select signal indicates when a command is transferring in formation to or from the device and the other signals are rel evant for the memory device. when the cs# signal is at the logic high state, the device is not selected and all input signals are ignored and all output sig nals are high impedance. the device will be in the st andby power mode, unless an internal embedded operation is in progress. an embedded operation is indicated by the status register 1 write-in-progress bit (sr1v[0] ) set to 1, until the operation is compl eted. some example embedded operations are: program, erase, or write registers (wrr) operations. driving the cs# input to the logic low stat e enables the device, placing it in the active power mode. after power-up, a falling edge on cs# is required prior to the start of any command. 3.5 serial input (si) / io0 this input signals used to transfer data serially into the device . it receives instructions, addresses, and data to be programm ed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sc k, in sdr commands, and on every edge of sck, in ddr commands). 3.6 serial output (so) / io1 this output signals used to transfer data serially out of the de vice. data is shifted out on the falling edge of the serial sck clock signal. so becomes io1 - an input and output during dual and quad commands for receiving addresses, and data to be programmed (values latched on rising edge of serial sck clock sig nal) as well as shifting out data (on the falling edge of sck in sdr commands, and on every edge of sck, in ddr commands). 3.7 write protect (wp#) / io2 when wp# is driven low (v il ), when the status register protect 0 (srp0_nv) or (srp0) bit of status r egister 1 (sr1nv[7]) or (sr1v[7]) is set to a 1, it is not possible to write to status registers, configuration registers or dlr registers. in this sit uation, the command selecting sr1nv, sr1v, cr1nv,cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv is ignored, and no error is set. this prevents any alteration of the legacy block protection settings. as a consequence, all the data bytes in the memory area t hat are protected by the legacy block protection feature are also ha rdware protected against data modification if wp# is low during commands changing status registers, configuration registers or dl r registers, with srp0_nv set to 1. similarly, the security region lock bits (lb3-lb0) are protected against programming. the wp# function is not available when the quad mode is enable d (cr1v[1]=1) or qpi mode is enabled (cr2v[3]=1). the wp# function is replaced by io2 for input and output during quad m ode or qpi mode is enabled (cr2v[3]=1) for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data on the falling edg e of sck, in sdr commands, and on every edge of sck, in ddr commands). wp# has an internal pull-up resistance; when unconnected, wp# is at v ih and may be left unconnected in the host system if not used for quad mode or qpi mode or protection. document number: 002-00124 rev. *f page 10 of 158 s25fl256l/S25FL128L 3.8 io3 / reset# io3 is used for input and output during quad mode (cr1v[1]=1) or qpi mode is enabled (cr2v[3]=1) for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge o f sck, in sdr commands, and on every edge of sck, in ddr commands). the io3 / reset# input may also be used to initiate the hardware reset function when the io3 / reset# feature is enabled by writing configuration regist er 2 non-volatile bit 7 (cr2nv[7]= 1). the input is only treated as reset# when the device is not in quad modes (114,144,444), cr1v[1] = 0, or when cs# is high. when quad modes are in use, cr1v[1]=1or qpi mode is enabled (cr2v[3]=1), and the device is selected with cs# low, the io3 / reset# is used only as io3 for information transfer. when cs# i s high, the io3 / reset# is not in use for in formation transfer and is used as the reset input. by co nditioning the reset operati on on cs# high during quad modes (114,144,444), the reset func tion remains available during quad modes (114,144,444). when the system enters a reset co ndition, the cs# signal must be driven high as part of t he reset process and the io3 / reset# signal is driven low. when cs# goes high the io3 / reset# in put transitions from being io3 to being the reset input. the reset condition is then detected when cs# remains high and the io3 / reset# signal remains low for t rp . if a reset is not intended, the system is required to actively drive io3 / reset# to high along with cs# being driven high at t he end of a transfer of data to the memory. following transfers of data to the host system, the memo ry will drive io 3 high during t cs . this will ensure that io3 / reset# is not left floating or being pulled slowly to high by the internal or an external passive pu ll-up. thus, an unintended reset is not triggered by the io3 / reset# not being recognized as high before the end of t rp . the io3 / reset# input reset feature is disabled when (cr2v[7]=0). the io3 / reset# input has an inte rnal pull-up resistor and may be left unconnected in the host system if not used for quad mod e or the reset function. the inte rnal pull-up will hol d io3 / reset# high after the host syst em has actively driven the signal hi gh and then stops driving the signal. note that io3 / reset# input c annot be shared by more than one spi-mio memory if any of them are operating in quad i/o mode as io3 being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the sam e io3 / reset# signal. 3.9 reset# the reset# input provides a hardware method of resetting the device to standby state, ready for receiving a command. when reset# is driven to logic low (v il ) for at least a period of t rp , the device starts the hardware reset process. reset# causes the same initialization process as is performed when power comes up and requires t pu time. reset# may be asserted low at an y time. to ensure data in tegrity any operation that was interru pted by a hardware reset should be reinitiated once the device is ready to accept a command sequence. reset# has an internal pull- up resistor and may be left unconn ected in the host system if not used. the intern al pull-up will h old reset high after the host system has actively driven the signal hi gh and then stops driving the signal. the reset# input is not available on all packages options. when not available the reset# input of th e device is tied to the ina ctive state. 3.10 voltage supply (v cc ) v cc is the voltage source for all device internal logic. it is th e single voltage used for all devi ce internal func tions including read, program, and erase. 3.11 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers. 3.12 not connected (nc) no device internal signal is connected to the package connector no r is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). 3.13 reserved for future use (rfu) no device internal signal is currently connected to the package connector but there is potential future use of the connector. i t is recommended to not use rfu connectors for pcb routing channe ls so that the pcb may take advantage of future enhanced features in compatib le footprint devices. document number: 002-00124 rev. *f page 11 of 158 s25fl256l/S25FL128L 3.14 do not use (dnu) a device internal signal may be connected to the package connecto r. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when th e signal is at v il . the signal has an inte rnal pull-down resistor and may be left unconnected in t he host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 4. block diagrams figure 6. logic block diagram 4.1 system block diagrams figure 7. bus master and memory devices on the spi bus ? single bit data path memory array control logic data path x decoders cs# sck si/io0 so/io1 reset#/io3 wp#/io2 reset# i/o y decoders data latch reset# wp# si sck cs# cs# wp# si sck cs2# cs1# spi bus master so spi flash spi flash reset# so document number: 002-00124 rev. *f page 12 of 158 s25fl256l/S25FL128L figure 8. bus master and memory devices on the spi bus ? dual bit data path figure 9. bus master and memory devices on th e spi bus ? quad bit data path ? separate reset# reset# wp# io1 sck cs# cs# wp# io1 sck cs2# cs1# spi bus master io0 spi flash spi flash reset# io0 reset# io3 io2 io1 sck cs# cs# io3 io2 io1 sck cs2# cs1# spi bus master io0 spi flash spi flash reset# io0 document number: 002-00124 rev. *f page 13 of 158 s25fl256l/S25FL128L figure 10. bus master and memo ry devices on the spi bus ? quad bit data path ? i/o3 / reset# io3 / reset# io2 io1 sck cs# io3 / reset# io2 io1 sck cs# spi bus master io0 spi flash io0 document number: 002-00124 rev. *f page 14 of 158 s25fl256l/S25FL128L 5. signal protocols 5.1 spi clock modes 5.1.1 single data rate (sdr) the fl-l family can be driven by an emb edded micro-controller (bus master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data i s always available from the falling edge of the sck clock signal. the difference between the two modes is t he clock polarity when the bus master is in standby mode and not transferring any data . ? sck will stay at logic low st ate with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 11. spi sdr modes supported timing diagrams throughout the remainder of the document are g enerally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram ma y show only mode 0 with sck low at the fall of cs#. in such a case, mode 3 timing simply means clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 3. sck cycles are measured (counted) from one falling edge of sc k to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already l ow at the beginning of a command. 5.1.2 double data rate (ddr) mode 0 and mode 3 are also supported for ddr commands. in ddr co mmands, the instruction bits ar e always latched on the rising edge of clock, the same as in sdr commands. however, the addre ss and input data that follow the instruction are latched on both the rising and falling edges of sck. the first address bit is latched on the first rising edge of sck following the falling edg e at the end of the last instruction bit. the first bit of output data is driven on the falling edge at the end of the last access latency ( dummy) cycle. sck cycles are measured (counted) in the same way as in sdr co mmands, from one falling edge of sck to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measur ed from the falling edge of cs# to the fi rst falling edge of sck because sck is already low at the beginning of a command. cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# si_io0 so_io1 msb msb document number: 002-00124 rev. *f page 15 of 158 s25fl256l/S25FL128L figure 12. spi ddr modes supported 5.2 command protocol all communication between the host system and fl-l family me mory devices is in the form of units called commands. see section 8., commands on page 60 for definition and details for all commands. all commands begin with an 8-bit instructi on that selects the type of information tr ansfer or device operation to be performed. commands may also have an address, instruction modifier, latency per iod, data transfer to the memo ry, or data transfer from the memory. all instruction, address, and data information is tran sferred sequentially between the host system and memory device. command protocols are also classified by a numerical nomenclatur e using three numbers to referenc e the transfer width of three command phases: ? instruction; ? address and instruction modifier (continuous read mode bits); ? data. single bit wide commands start with an instruction and may provide an address or data, all sent only on the si signal. data may be sent back to the host serially on the so signal. this is refere nced as a 1-1-1 command protocol for single bit width instructio n, single bit width address and modifier, single bit data. dual-o or quad-o commands prov ide an address sent from the host as serial on si (io0) then fo llowed by dummy cycles. data is returned to the host as bit pairs on io0 and io1 or, four bit (nibbl e) groups on io0, io1, io2, and io3. this is referenced as 1-1-2 for dual-o and 1-1-4 for quad-o command protocols. dual or quad input / output (i/o ) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibb le) groups on io0, io1, io2, and io 3 then followed by dummy cycles. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. this is referenced as 1-2-2 for dual i/o and 1-4-4 for quad i/o command protocols. the fl-l family also supports a qpi mode in which all informati on is transferred in 4-bit width, including the instruction, add ress, modifier, and data. this is refer enced as a 4-4-4 command protocol. commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip select (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an eight bit (byte) instruction. the instruction selects the type of information transfer or device operation to be performed. the instruction transfers occur on sck rising edges. however, some read commands are modified by a prior read command, such t hat the instruction is impli ed from the earlier command. this is called continuous read mode. when the device is in continuous read mode, the in struction bits are not transmitted at the beginning of the command because the instruction is the same as the read command that initiated the continuous read mode. in continuous read mode the command will begin with the read address. thus, continuous read mode removes eight instruction bits from each read command in a series of same type read commands. cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# transfer_phase io0 io1 io2 io3 inst. 7 inst. 0 a28 a24 a0 m4 m0 dl p . dl p . d0 d1 a29 a25 a1 m5 m1 dl p . dl p . d0 d1 a30 a26 a2 m6 m2 dl p . dl p . d0 d1 a31 a27 a3 m7 m3 dl p . dl p . d0 d1 dummy / dlp address mode instruction document number: 002-00124 rev. *f page 16 of 158 s25fl256l/S25FL128L ? the instruction may be stand alone or may be followed by address bi ts to select a location within one of several address spaces in the device. the instruction determines the address space used. the address may be either a 24 bit or a 32 bit, byte boundary, address. the address transfers occur on sck ri sing edge, in sdr commands, or on every sck edge, in ddr commands. ? in legacy spi mode, the width of all transfers following the instruction are determined by the instruction sent. following transfers may continue to be single bit serial on only the si or serial output (so) signals, they may be done in two bit groups per (dual) transfer on the io0 and io 1 signals, or they may be done in 4 bi t groups per (quad) transfer on the io0- io3 signals. within the dual or quad groups the least significant bit is on io0. more significant bits are placed in significan ce order on each higher numbered io signal. single bits or parallel bit groups are transferred in most to least significant bit order. ? in qpi mode, the width of all transfers is a 4- bit wide (quad) transfer on the io0-io3 signals. ? dual and quad i/o read instructions send an instruction m odifier called continuous read mode bits, following the address, to indicate whether the next command will be of the same ty pe with an implied, rather than an explicit, instruction. these mode bits initiate or end the continuous read mode. in cont inuous read mode, the next command thus does not provide an instruction byte, only a new address and mode bits. this re duces the time needed to send each command when the same command type is repeated in a sequence of commands. th e mode bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? sck continues to toggle duri ng any read access latency pe riod. the latency may be zero to several sck cycles (also referred to as dummy cycles). at the end of the read latency cycl es, the first read data bits are driven from the outputs on sck falling edge at th e end of the last read latency cycle. the first read data bi ts are considered transf erred to the host on the following sck rising edge. each following transfer occurs on the next sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? if the command returns read data to the host, the device continues sending dat a transfers until the host takes the cs# signal high. the cs# signal can be driven high after any tr ansfer in the read data sequence. this will terminate the command. ? at the end of a command that does not return data, the host dr ives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone instruction or , of the last write data byte that is tr ansferred. that is, the cs# signal must be driven high when the number of bits after the cs# signal was driv en low is an exact multiple of eight bits. if the cs# signal does not go high exactly at the eight bit boundary of the instruction or write data, the command is rejected and not executed. ? all instruction, address, and mode bits are shifted into the devi ce with the most significant bits (msb) first. the data bits a re shifted in and out of the device msb first. all data is transferred in byte units wi th the lowest addre ss byte sent first. following bytes of data are sent in lowest to highes t byte address order i.e. the byte address increments. ? all attempts to read the flas h memory array during a program, erase, or a write cycle (embedded op erations) are ignored. the embedded operation will continue to ex ecute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command co mpletes execution and whether the command was successful. document number: 002-00124 rev. *f page 17 of 158 s25fl256l/S25FL128L 5.2.1 command sequence examples figure 13. stand alone instruction command figure 14. single bit wide input command figure 15. single bit wide output command without latency figure 16. single bit wide i/o command with latency figure 17. dual output read command cs# sck si_io0 so_io1-io3 phase 7 6 5 4 3 2 1 0 instruction cs# sclk so_io1-io3 so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 2 cs# sclk si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 31 1 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address dummy cycles data 1 data 2 document number: 002-00124 rev. *f page 18 of 158 s25fl256l/S25FL128L figure 18. quad output read command figure 19. dual i/o command figure 20. quad i/o command note: the gray bits are optional, the host do es not have to drive bits during that cycle. figure 21. quad i/o read command in qpi mode note: the gray bits are optional, the host do es not have to drive bits during that cycle. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 31 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address dummy d1 d2 d3 d4 d5 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 4 0 4 0 4 0 4 0 29 5 1 5 1 5 1 5 1 5 1 5 1 30 6 2 6 2 6 2 6 2 6 2 6 2 31 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 phase 4 0 28 4 0 4 0 4 0 4 0 4 0 4 0 5 1 29 5 1 5 1 5 1 5 1 5 1 5 1 6 2 30 6 2 6 2 6 2 6 2 6 2 6 2 7 3 31 7 3 7 3 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4 document number: 002-00124 rev. *f page 19 of 158 s25fl256l/S25FL128L figure 22. ddr quad i/o read command note: 1. the gray bits are optional, the host does not have to drive bits during that cycle. figure 23. ddr quad i/o read command qpi mode note: 1. the gray bits are optional, the host does not have to drive bits during that cycle. additional sequence diagrams, specific to each command, are provided in section 8. commands on page 60 . cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2 cs# sclk io0 io1 io2 io3 phase 4 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 5 1 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 6 2 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 7 3 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruct. address mode dummy dlp d1 d2 document number: 002-00124 rev. *f page 20 of 158 s25fl256l/S25FL128L 5.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend ? z = no driver - floating signal ? hl = host driving v il ? hh = host driving v ih ? hv = either hl or hh ? x = hl or hh or z ? ht = toggling between hl and hh ? ml = memory driving v il ? mh = memory driving v ih ? mv = either ml or mh table 3. interface states summary interface state vcc sck cs# reset# io3 / reset# wp# / io2 so / io1 si / io0 power-off document number: 002-00124 rev. *f page 22 of 158 s25fl256l/S25FL128L 5.3.8 single latency (dummy) cycle read commands may have zero to several latency cycles during wh ich read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the conf iguration register (cr3v[3:0]) . during the latency cycles, the host keeps reset# and io3 / r eset# high, cs# low and sck toggl es. the write protect (wp#) signal is ignored . the host may drive the si signal during these cycles or the host may leave si float ing. the memory does not use any data driven on so or other i/o signals during the latency cycl es. the memory does not drive th e serial output (so) or i/o signals during the latency cycles. the next interface state depends on the comm and structure i.e. the number of latency cycles, and whether the read is single, du al, or quad width. 5.3.9 single output cycle ? memory to host transfer several commands transfer information back to the host on the sing le serial output (so) signal. the host keeps reset# and io3 / reset# high, cs# low. the write protect (wp#) sig nal is ignored. the memory ignores the serial input (si) signal. the memory drives so with data. the next interface state continues to be single output cycle until the host returns cs# to high ending the command. 5.3.10 dual input cycle ? host to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps reset# and io3 / reset# high, cs# low. the writ e protect (wp#) signal is ignored. the host drives address on si / io0 and so / io1. the next interface st ate following the delivery of address a nd mode bits is a dual latency c ycle if there are latency cycles ne eded or dual output cycle if no latency is required. 5.3.11 dual latency (dummy) cycle read commands may have zero to several latency cycles during wh ich read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the conf iguration register (cr3v[3:0]) . during the latency cycles, the host keeps reset# and io3 / r eset# high, cs# low, and sck co ntinues to toggle. the write protect (wp#) signal is ignored. the host may drive the si / io0 and so / io1 signals during these cycles or the host may leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 and so / io1 during the latency cycles. the host must stop driving si / io0 and so / io1 on t he falling edge of sck at the end of the last latency cycl e. it is recomm ended that the host stop driving them during all latency cyc les so that there is sufficient time for the host drivers to turn off before the m emory begins to drive at the end of the latency cycles. this prevents driver conflict between host and me mory when the signal directi on changes. the memory do es not drive the si / io0 and so / io1 signals during th e latency cycles. the next interface state fo llowing the last la tency cycle is a du al output cycle. 5.3.12 dual output cycle ? memory to host transfer the read dual output and read d ual i/o return data to the host two bits in each cycle. t he host keeps reset # and io3 / reset# high, cs# low. the write protect (wp#) signa l is ignored. the memory drives data on the si / io0 and so / io1 signals during the dual output cycles on the falling edge of sck. the next interface state continues to be dual output cycl e until the host returns cs# to high ending the command. 5.3.13 qpp or qor address input cycle the quad page program and quad output read commands send addres s to the memory only on io0. the other io signals are ignored. the host keeps reset# and io3 / reset# high, cs# low, and drives io0. for qpp the next interface state following the delivery of address is the quad input cycle. for qor the next interface state fo llowing address is a quad latency cycle if there are latency cyc les needed or quad output cycle if no latency is required. 5.3.14 quad input cycle ? host to memory transfer the quad i/o read command transfers four address or mode bits to the memory in each cycle. in qpi mode the quad i/o read and page program commands transfer four data bits to the memory in each cycle, includi ng the instruction cycles . the host keeps cs# low, and drives the io signals. document number: 002-00124 rev. *f page 23 of 158 s25fl256l/S25FL128L for quad i/o read the next interface state fo llowing the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. for qpi mode page program, the host returns cs# high following the delivery of data to be programme d and the interface retu rns to standby state. 5.3.15 quad latency (dummy) cycle read commands may have zero to several latency cycles during wh ich read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the conf iguration register (cr3v[3:0]) . during the latency cycles, the host keeps cs# low and continues to toggle sck. the host may drive the io signals during these cycles or the host may leave the io floating. the memory does not use any data driven on io during the latency cycles. the host must stop driving the io signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so t hat there is sufficie nt time for the host drivers to turn off before the memory begins to dr ive at the end of the latency cycles. this prevents dr iver conflict between host and memory wh en the signal direction changes. the memory does not drive the io signals during the latency cycles. the next interface state following the la st latency cycle is a quad output cycle. 5.3.16 quad output cycle ? memory to host transfer the quad-o and quad i/o read returns data to the host four bits in each cycle. the host keeps cs# low. the memory drives data on io0-io3 signals during the quad output cycles. the next interface state continues to be quad output c ycle until the host returns cs# to high ending the command. 5.3.17 ddr quad input cycle ? host to memory transfer the ddr quad i/o read command sends address, and mode bits to the memory on all the io signals . four bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps cs# low. the next interface state following the delivery of address and mode bits is a ddr latency cycle. 5.3.18 ddr latency cycle ddr read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the configuration register (cr3v[3:0]). during the latency cycles, the host keeps cs# low. the host may not drive the io signals during these cycles. so t hat there is sufficient time for the host drivers to turn off before the memory begins to dr ive. this prevents driver conflict betw een host and memory when the signal direction changes. the memory has an option to drive all the io signals with a data learning pattern (dlp) during the last 4 latency cycles. t he dlp option should not be enabled when there are fewer than five latency cycles so t hat there is at least one cycle of high impeda nce for turn around of the io signals before the memory begins driving the dlp. when there are more than 4 cycles of latency the memory does not drive the io signals unt il the last four cycles of latency. the next interface state following the last latency cycle is a ddr quad output cycle, depending on the instruction. 5.3.19 ddr quad output cycle ? memory to host transfer the ddr quad i/o read command returns bits to the host on all t he io signals. four bits are transferred on the rising edge of s ck and four bits on the falling edge in each cycle. the host keeps cs# low. the next interface state continues to be ddr quad output cycle until the host returns cs# to high ending the command. document number: 002-00124 rev. *f page 24 of 158 s25fl256l/S25FL128L 5.4 data protection some basic protection against unintended changes to stored data are provided and controlled purel y by the hardware design. thes e are described below. other software managed protection method s are discussed in the software section of this document. 5.4.1 power-up the device must not be selected at power-up (that is, cs# must follow the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu user is not allowed to enter any command until a valid delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 131 . however, correct operation of the device is not guaranteed if v cc returns below v cc (min) during t pu . no command should be sent to the device until the end of t pu . 5.4.2 low power when v cc is less than v cc (cut-off) the memory device will ignore commands to en sure that program and erase operations can not start when the core supply volta ge is out of the operating range. 5.4.3 clock pulse count the device verifies that all non-volatile memory and register da ta modifying commands consist of a clock pulse count that is a multiple of eight bit transfers (byte boundar y) before executing them. a command not end ing on an 8 bit (byte) boundary is igno red and no error status is set for the command. 5.4.4 deep power down (dpd) in dpd mode the device responds only to the resume from dp d command (res abh). all other commands are ignored during dpd mode, thereby protecting the memory from program and erase operations. if the io3 / reset# function has been enabled (cr2v[7]=1) or if reset# is ac tive, io3 / reset# or reset# going low will start a hardware reset and re lease the device from dpd mode. document number: 002-00124 rev. *f page 25 of 158 s25fl256l/S25FL128L 6. address space maps 6.1 overview 6.1.1 extended address the fl-l family supports 32 bit (4 byte) addresses to enable hi gher density devices than allowed by previous generation (legacy) spi devices that supported only 24 bit (3 byte) addresses. a 24 bi t, byte resolution, address can access only 16 mbytes (128 mb) maximum density. a 32 bit, byte resolution, address allows direct addressing of up to a 4 gb ytes (32 gbits) address space. legacy commands continue to support 24 bit addresses for backwar d software compatibility. extended 32 bit addresses are enabled in two ways: ? extended address mode ? a volatile config uration register bit that changes all legacy commands to expect 32 bits of address supplied from the host system. ? 4 byte address commands ? that perform both legacy and ne w functions, which always expect 32 bit address. the default condition for extended address mode, after power-up or reset, is controlled by a non- volatile configuration bit. th e default extended address mode may be set for 24 or 32 bit addresse s. this enables legacy software compatible access to the firs t 128 mb of a device or for the device to start directly in 32 bit address mode. 6.1.2 multiple address spaces many commands operate on the main flash memory array. some commands operate on address spac es separate from the main flash array. each separate address space uses the full 24 or 32 bit address but may only define a small portion of the availabl e address space. 6.2 flash memory array the main flash array is divided into uniform erase units called physical blocks (64 kb), half blocks (32 kb) and sectors (4 kb) . table 4. s25fl256l sector address map block size (kbyte) block count block range half block size (kbyte) half block count half block range sector size (kbyte) sector count sector range address range (byte address) notes 64 1 ba00 32 1 hba00 4 1 sa00 0000000h- 0000fffh sector starting address ? sector ending address ::: : 32 2 hba01 4 16 sa15 000f000h- 000ffffh ::: : : : ::: : 64 512 ba511 32 1023 hba1022 4 8176 sa8175 1ff0000h- 1ff0fffh ::: : 32 1024 hba1023 4 8192 sa8191 1fff000h- 1ffffffh document number: 002-00124 rev. *f page 26 of 158 s25fl256l/S25FL128L table 5. S25FL128L sector address map 6.3 id address space the rdid command (9fh) reads information from a separate flas h memory address space for dev ice identification (id). see section 10.2, device id address map on page 127 for the tables defining the contents of the id address space. the id address space is programmed by cypress and read-only fo r the host system. 6.3.1 device unique id a 64-bit unique number is located in 8 bytes of the unique device id address space, see table 51, unique device id on page 127 . this unique id may be used as a software readable serial number that is unique for each device. 6.4 jedec jesd216 serial flash disc overable parameters (sfdp) space the rsfdp command (5ah) reads information from a separate flash memory address space for device identification, feature, and configuration information, in accord with the jedec jesd216 st andard for serial flash discoverable parameters. the id address space is incorporated as one of the sfdp parameters. see section 10.1, jedec jesd216b serial flash discoverable parameters on page 119 for the tables defining the contents of the sfdp address space. the sfdp address spac e is programmed by cypress and read-only for the host system. 6.5 security regions address space each fl-l family memory device has a 1024 byte security regions address space that is separate from the main flash array. the security regions area is divided into 4, individually lockable 256 byte regions. the security regions memory space is intended to hold information that can be tempor arily protected or permanently lock ed from further program or erase. the regions data bytes are erased to ffh when shipped from cypr ess. the regions may be programmed and erased like any other flash memory address space when not protected or locked. each regi on can be individually erased. the security region lock bits (cr1nv[5:2]) are located in the configurat ion register 1. the security region lock bits are one time programmable (otp) and after being programmed (set to 1) a lock bit permanently prot ects the related region from further erase or programming. regions 2 and 3 also have temporary protecti on from program or erase by the protection register (pr) nvlock bit. the nvlock bit is volatile and set or cleared by the irp logic and commands. see protection register (pr) on page 42 . the security region password protection bit in the irp register (irp[2]) allows regions 2 and 3 to be protected from program an d erase operations until a password is provided. the security region read protection bit in the irp register (irp[6]) allows regi on 3 to also be protected from read operations until a password is prov ided. attempting to read in a region, that is protected from read, returns invalid and undefined data. see individual and region protection register (irp) on page 40 . attempting to erase or program in a region t hat is locked or protected will fail with the p_err or e_err bit in sr2v[6:5] set t o ?1?. (see status register 2 volatile (sr2v) on page 31 for detail descriptions). block size (kbyte) block count block range half block size (kbyte) half block count half block range sector size (kbyte) sector count sector range address range (byte address) notes 64 1 ba00 32 1 hba00 4 1 sa00 000000h-000fffh sector starting address ? sector ending address ::: : 32 2 hba01 4 16 sa15 00f000h-00ffffh ::::::::: : 64 256 ba255 32 511 hba510 4 4080 sa4079 ff0000h- ff0fffh ::: : 32 512 hba511 4 4096 sa4095 fff000h- ffffffh document number: 002-00124 rev. *f page 27 of 158 s25fl256l/S25FL128L 6.6 registers registers are small groups of memory cells used to configure how the fl-l family memo ry device operates or to report the status of device operations. the registers are access ed by specific commands. the commands (and hexadecimal instruct ion codes) used for each register are noted in each register description. in legacy spi memory devices the individual register bits coul d be a mixture of volatile, non-v olatile, or one time programmabl e (otp) bits within the same register. in so me configuration options the type of a regi ster bit could change e.g. from non-volati le to volatile. the fl-l family uses separate non-volatile or volatile memory cell groups (areas) to implement the different register bit types . however, the legacy registers and commands continue to appear and behave as they always have for legacy software compatibility. there is a non-volatile and a volatile version of each legacy regi ster when that legacy register has volatile bits or when the command to read the legacy register has zero read latency. when such a r egister is read the volatile vers ion of the register is deliver ed. during power-on reset (por), hardware reset, or software reset, the non-v olatile version of a register is copied to the volatile versi on to provide the default state of the volatile register. when non-volatile register bi ts are written the non-v olatile version of the register is erased and programmed with the new bit values and the volatile ve rsion of the register is update d with the new c ontents of the non- volatile version. when otp bits are program med the non-volatile version of the register is programmed and the appropriate bits are updated in the volatile version of the register. when volatile register bits are written, only the volatile version of the regi ster has the appropriate bits updated. the type for each bit is noted in each register description. the default state shown for each bit refers to the state after pow er-on reset, hardware reset, or software reset if the bit is volatile . if the bit is non-volatile or otp, the default state is the va lue of the bit when the device is shipped from cypress. 6.6.1 status register 1 6.6.1.1 status register 1 non-volatile (sr1nv) s25fl256l related commands: non-volatile write enable (wren 06h), wr ite disable (wrdi 04h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). table 6. security region address map region byte address range (hex) initial delivery state (hex) region 0 000 to 0ff all bytes = ff region 1 100 to 1ff all bytes = ff region 2 200 to 2ff all bytes = ff region 3 300 to 3ff all bytes = ff table 7. status register 1 non-volatile (sr1nv) bits field name function type default state description 7 srp0_nv status register protect 0 default non-volatile 0 provides t he default state for srp0. 6 tbprot_nv tbprot default non-volatile 0 provides t he default state for tbprot 5 bp_nv3 legacy block protection default non-volatile 0000b provides t he default state for bp bits. 4 bp_nv2 3 bp_nv1 2 bp_nv0 1 wel_d wel default non-volatile read only 0 provides the default stat e for the wel status. not user programmable. 0 wip_d wip default non-volatile read only 0 provides the default stat e for the wip status. not user programmable. document number: 002-00124 rev. *f page 28 of 158 s25fl256l/S25FL128L status register protect non-volatile (srp0_nv) sr1nv[7] : provides the default state for srp0. see status register protect (srp1, srp0) on page 47 . top or bottom protection (tbprot_nv) sr1nv[6]: provides the default state for tbprot. legacy block protection (bp_nv3, bp_nv2, bp_nv1, bp_nv0) sr1nv[5:2] : provides the default state for bp_3 to bp_0 bits. write enable latch de fault (wel_d) sr1nv[1] : provides the default state for the wel st atus in sr1v[1]. this bit is programmed by cypress and is not user programmable. write in progress default (wip_d) sr1nv[0] : provides the default state fo r the wip status in sr1v[0]. this bit is programmed by cypress and is not user programmable. 6.6.1.2 status register 1 volatile (sr1v) s25fl256l related commands: read status register 1 (rdsr1 05h), write e nable for volatile (wrenv 50h), write registers (wrr 01h), clear status register (clsr 30h), read any register (rdar 65h) , write any register (wrar 71h). this is the register displayed by the rdsr1 command status register protect 0 (srp0) sr1v[7]: places the device in the hardware protect ed mode when this bit is set to 1 and the wp# input is driven low. in this mode, an y commands that change status registers or configuration registers are ignored and not accepted for execution, effectively locking the state of the status registers and co nfiguration registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv bits, by making the registers read-only. if wp# is high, status registers and configuration registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2 v, cr3nv, dlrnv and dlrv may be changed. if srp0 is 0, wp# has no effect, the status registers and configuration registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv may be changed. wp# has no effect on the writing of any other registers. srp0 tracks any changes to the non- volatile version of this bit (srp0_nv). w hen qpi or qio mode is enabled (cr2v[3] or cr1v[1] = ?1?) the internal wp# signal leve l is = 1 because the wp# external input is used as io2 when either mode is active. this effectiv ely turns off hardware protection . the register sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are unlocked and can be written. see status register protect (srp1, srp0) on page 47 . table 8. s25fl256l status register 1 volatile (sr1v) bits field name function type default state description 7 srp0 status register protect 0 volatile sr1nv 1 = locks state of sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv when wp# is low, by not executing any command that would affect sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv 0 = no register protection, even when wp# is low. 6 tbprot top or bottom relative protection volatile 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 5 bp3 legacy block protection volatile volatile protects the selected range of se ctors (blocks) from program or erase. 4 bp2 3 bp1 2 bp0 1 wel write enable latch volatile read only 0 = not write enabled, no embedded operation can start, 1= write enable, embedded operation can start this bit is not affected by wrr or wrar, only wren, wrenv, wrdi and clsr commands affect this bit. 0 wip write in progress volatile read only 1 = device busy, an embedded operation is in progress such as program or erase 0 = ready device is in standby mode and can accept commands this bit is not affected by wrr or wrar, it only prov ides wip status. document number: 002-00124 rev. *f page 29 of 158 s25fl256l/S25FL128L tbprot sr1v[6]: this bit defines the refe rence point of the legacy block protection bits bp3, bp2, bp1, and bp0 in the status register. as described in the status register section, the bp3-0 bits allow the user to optionally protect a portion of the arr ay, ranging from 1/64, ?, ?, etc., up to the entire a rray. when tbprot is set to a ?0? the legacy block protection is defined to start from the top (maximum address) of the array. when tbprot is set to a ?1? the leg acy block protection is defined to start from the bottom (ze ro address) of the array. tbprot tracks any changes to the non-volatile version of this bit (tbprot_nv). legacy block protection (bp3, bp2, bp1, bp0) sr1v[5:2] : these bits define the main flash array area to be protected against program and erase commands. see section 7.6.1, legacy block protection on page 48 for a description of how the bp bit values select the memory array area protected. write enable latch (wel) sr1v[1] : the wel bit must be set to 1 to enable program , write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the writ e enable (wren) command execution sets the write enable latch to a ?1? to allow any program, erase, or write commands to execute afte rwards. the write disable (wrdi) command can be used to set the write enable latch to a ?0? to prevent all program, erase, and wr ite commands from execution. th e wel bit is cleared to 0 at the end of any successful program, write, or erase operation. fo llowing a failed operation the wel b it may remain set and should be cleared with a clsr command. after a power down / power up sequence, hardware reset, or software reset, the write enable latch is set to a wel_d. th e wrr or wrar command does not affect this bit. write in progress (wip) sr1v[0] : indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a ?1? the device is busy performing an operation. while wip is ?1?, only read status registers (rdsr1, rdsr2), read any register (rdar), erase / program suspend (eps), clear status register (clsr), read configuration re gisters (rdcr1, rdcr2, rdcr3) and software reset (rsten 66h followed by rst 99h) commands are accepted. eps command will only be accepted if memory array erase or program operations are in progress. the status register e_err and p_err bits are updated while wip =1. when p_err or e_err bits are set to one, the wip bit will remain set to one indicating the device remain s busy and unable to receive new operation commands. a clear sta tus register (clsr) command must be received to return the device to standby mode. when the wip bit is cleared to 0 no operation is in progress. this is a read-only bit. 6.6.1.3 status register 1 non-volatile (sr1nv) S25FL128L related commands: non-volatile write enable (wren 06h), wr ite disable (wrdi 04h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h) status register protect non-volatile (srp0_nv) sr1nv[7] : provides the default state for srp0. see status register protect (srp1, srp0) on page 47 . sector / block protect (sec_nv) sr1nv[6]: provides the default state for sec. top or bottom protection (tbprot_nv) sr1nv[5]: provides the default state for tbprot. legacy block protection (bp_nv3, bp_nv2, bp_nv1, bp_nv0) sr1nv[4:2] : provides the default state for bp_2 to bp_0 bits. table 9. S25FL128Lstatus register 1 non-volatile (sr1nv) bits field name function type default state description 7 srp0_nv status register protect 0 default non-volatile 0 provides the default state for srp0. 6 sec_nv sector / block protect non-volatile 0 provides the defaults state for sec 5 tbprot_ nv tbprot default non-volatile 0 provides the default state for tbprot 4 bp_nv2 legacy block protection default non-volatile 000b provides the default state for bp bits. 3 bp_nv1 2 bp_nv0 1 wel_d wel default non-volatile read only 0 provides the default state for the wel status. not user programmable. 0 wip_d wip default non-volatile read only 0 provides the default state fo r the wip status. not user programmable. document number: 002-00124 rev. *f page 30 of 158 s25fl256l/S25FL128L write enable latch de fault (wel_d) sr1nv[1] : provides the default state for the wel st atus in sr1v[1]. this bit is programmed by cypress and is not user programmable. write in progress default (wip_d) sr1nv[0] : provides the default state fo r the wip status in sr1v[0]. this bit is programmed by cypress and is not user programmable. 6.6.1.4 status register 1 volatile (sr1v) S25FL128L related commands: read status register 1(rdsr1 05h), write en able for volatile (wrenv 5 0h), write registers (wrr 01h), clear status register (clsr 30h), read any register (rdar 65h) , write any register (wrar 71h). this is the register displayed by the rdsr1 command. status register protect 0 (srp0) sr1v[7]: places the device in the hardware protect ed mode when this bit is set to 1 and the wp# input is driven low. in this mode, an y command that change status registers or configuration r egisters are ignored and not accepted for execution, effectively locking the state of the status registers and co nfiguration registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv bits, by making the registers read-only. if wp# is high, status registers and configuration registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv may be changed and configuration registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv may be changed. wp# has no effect on the writing of any other registers. srp0 tracks any change s to the non-volatile version of this bit (srp0_nv). when q pi or qio mode is enabled (cr2v[3] or cr1v[1] = ?1?) the internal wp# signal level is = 1 bec ause the wp# external input is used as i o2 when either mode is active. this effectively turns off hardwa re protection. the register sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are unlocked and can be written. see status register protect (srp1, srp0) on page 47 . sector / block prot ect (sec) sr1v[6]: this bit controls if the block protect bits (bp2, bp1, bp0) protect ei ther 4kb sectors (sec = ?1?) or 64kb blocks (sec = ?0?). see section 7.6.1, legacy block protection on page 48 for a description of how the sec bit value select the memory array area protected. table 10. S25FL128L status register 1 volatile (sr1v) bits field name function type default state description 7 srp0 status register protect 0 volatile sr1nv 1 = locks state of sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv when wp# is low, by not executing any commands that would affect sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv 0 = no register protection, even when wp# is low. 6 sec sector / block protect volatile 0 = bp2-bp0 protect 64kb blocks 1 = bp2-bp0 protect 4kb sectors 5 tbprot top or bottom relative protection volatile 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 4 bp2 legacy block protection volatile volatile protects the selected range of sectors (blocks) from program or erase. 3 bp1 2 bp0 1 wel write enable latch volatile read only 0 = not write enabled, no embedded operation can start, 1= write enable, embedded operation can start this bit is not affected by wrr or wrar, only wren wrenv, wrdi and clsr commands affect this bit. 0 wip write in progress volatile read only 1 = device busy, an embedded operation is in progress such as program or erase 0 = ready device is in standby mode and can accept commands this bit is not affected by wr r or wrar, it only provides wip status. document number: 002-00124 rev. *f page 31 of 158 s25fl256l/S25FL128L tbprot sr1v[5]: this bit defines the reference point of the legacy bl ock protection bits bp2, bp1, and bp0 in the status register. as described in the status register section, the bp2-0 bits allow the user to optionally protect a portion of the arr ay, ranging from 1/64, ?, ?, etc., up to the entire a rray. when tbprot is set to a ?0? the legacy block protection is defined to start from the top (maximum address) of the array. when tbprot is set to a ?1? the leg acy block protection is defined to start from the bottom (ze ro address) of the array. tbprot tracks any changes to the non-volatile version of this bit (tbprot_nv). legacy block protection (bp2, bp1, bp0) sr1v[4:2] : these bits define the main flash ar ray area to be protected against program and erase commands. see section 7.6.1, legacy block protection on page 48 for a description of how the bp bit values select the memory array area protected. write enable latch (wel) sr1v[1] : the wel bit must be set to 1 to enable program , write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the writ e enable (wren) command execution sets the write enable latch to a ?1? to allow any program, erase, or write commands to execute afte rwards. the write disable (wrdi) command can be used to set the write enable latch to a ?0? to prevent all program, erase, and wr ite commands from execution. th e wel bit is cleared to 0 at the end of any successful program, write, or erase operation. fo llowing a failed operation the wel b it may remain set and should be cleared with a clsr command. after a power down / power up sequence, hardware reset, or software reset, the write enable latch is set to a wel_d. th e wrr or wrar command does not affect this bit. write in progress (wip) sr1v[0] : indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a ?1? the device is busy performing an operation. while wip is ?1?, only read status (rdsr1 or rd sr2), read any register (rdar), erase / program suspend (eps), clear status register (clsr), and software reset (rsten 66h followed by rst 99h) commands are accepted. eps command will only be accepted if memory array erase or program operations ar e in progress. the status register e_err and p_err bits are updated while wip =1. when p_err or e_err bits are set to one, th e wip bit will remain set to one indicating the device remains busy and unable to receive new operation commands. a clear status register (clsr) command must be received to return the device to standby mode. when the wip bit is cleared to 0 no operation is in progress. this is a read-only bit. 6.6.2 status register 2 volatile (sr2v) related commands: read status register 2 (rdsr2 07h), read any register (rdar 65h). status r egister 2 does not have user programmable non-volatile bits, all defined bits are volatile read only status. the default state of these bits are set by hard ware. erase error (e_err) sr2v[6] : the erase error bit is used as an erase operat ion success or failure indication. when the erase error bit is set to a ?1? it indicates that there was an error in the last erase operation. this bit will also be set when the user attempts to erase an individual protected main memory sector or erase a locked security region. the chip erase command will set e_err if a protected sector is found during the command execution. when the erase error bit is set to a ?1? this bit can be cleared to z ero with the clear status register (clsr) command. this is a read- only bit and is not affected by the wrr or wrar commands. table 11. status register 2 volatile (sr2v) bits field name function type default state description 7 rfu reserved 0 reserved for future use 6 e_err erase error occurred volatile read only 0 1 = error occurred 0 = no error 5 p_err programming error occurred volatile read only 0 1 = error occurred 0 = no error 4 rfu reserved 0 reserved for future use 3 rfu reserved 0 reserved for future use 2 rfu reserved 0 reserved for future use 1 es erase suspend volatile read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile read only 0 1 = in program suspend mode. 0 = not in program suspend mode. document number: 002-00124 rev. *f page 32 of 158 s25fl256l/S25FL128L program error (p_err) sr2v[5] : the program error bit is used as a program oper ation success or failure indication. when the program error bit is set to a ?1? it indicates that there was an error in the last program operation. this bit will also be set when the user attempts to program within a protected main memory sect or, or program within a locked security region. when the program error bit is set to a ?1? this bit can be cleared to zero with the clear status register (clsr) command. this is a read-only bi t and is not affected by the wrr or wrar commands. erase suspend (es) sr2v[1] : the erase suspend bit is used to determine when the device is in erase suspend mode. this is a status bit that cannot be written by the us er. when erase suspend bit is set to ?1?, the device is in erase suspend mode. when erase suspend bit is cleared to ?0?, the device is not in erase suspend mode. refer to section 8.6.5, program or erase suspend (pes 75h) on page 98 for details about the erase suspend/resume commands. program suspend (ps) sr2v[0]: the program suspend bit is used to determine when the device is in program suspend mode. this is a status bit that cannot be writte n by the user. when program suspend bit is se t to ?1?, the device is in program suspe nd mode. when the program suspend bit is cleared to ?0?, the device is not in program suspend mode. refer to section 8.6.5, program or erase suspend (pes 75h) on page 98 for details. 6.6.3 configuration register 1 configuration register 1 controls certain interface and data prot ection functions. the register bits can be changed using the w rr command with sixteen input cycles or with the wrar command. 6.6.3.1 configuration register 1 non-volatile (cr1nv) related commands: non-volatile write e nable (wren 06h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). suspend erase/program status (sus_d) cr1nv[7]: provides the default state for the sus bi t in cr1v[7]. this bit is not user programmable. complement protect (cmp_nv) cr1nv[6]: provides the default state for the cmp bit in cr1v[6]. security region lock bits (lb3, lb2, lb1, lb0) cr1nv[5:2]: provide the otp write protection control of the security regions. when an lb bit is set to 1 the related security region can no longer be programmed or erased. quad data width non-volatile (quad_nv) cr1nv[1] : provides the default state for th e quad bit in cr1v[1]. the wrr or wrar command affects this bit. programming cr1nv[1] =1 will default operation to allow quad-data-width commands at power-on or reset. status register protect 1 default (srp1_d) cr1nv[0] : provides the default state for the srp1 bit in cr1v[0]. when irp[2:0]= ?111? the srp1_d otp bit is user programmable. w hen srp1_d =?1? registers sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are permanently locked. see status register protec t (srp1, srp0) on page 47 . table 12. configuration register 1 non-volatile (cr1nv) bits field name function type default state description 7 sus_d suspend status default non-volatile read only 0 provides the default state for the suspend status. not user programmable. 6 cmp_nv complement protection default non-volatile 0 provides the default state for cmp. 5 lb3 security region lock bits otp 0 otp lock bits 3:0 for security regions 3:0 0 = security region not locked 1 = security region permanently locked 4 lb2 0 3 lb1 0 2 lb0 0 1 quad_nv quad default non-volatile 0 provides the default state for quad. 0 srp1_d status register protect 1 default otp 0 when irp[2:0] = ?111? srp1_d bit is programmable. lock current state of sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv 1 = registers permanently locked 0 = registers not protected by srp1 after por document number: 002-00124 rev. *f page 33 of 158 s25fl256l/S25FL128L 6.6.3.2 configuration register 1 volatile (cr1v) related commands: read configuration regist er 1 (rdcr1 35h), write enable for vola tile (wrenv 50h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). this is the register displayed by the rdcr1 command. suspend status (sus) cr1v[7] : the suspend status bit is used to determine when the device is in erase or program suspend mode. this is a status bit that cannot be written by the user. when suspend status bit is set to ?1?, the device is in erase or program suspend mode. when suspend status bit is cleared to ?0?, th e device is not in erase or program suspend mode. refer to section 8.6.5, pr ogram or erase suspend (pes 75h) on page 98 for details about the er ase/program suspend/resume commands. complement protection (cmp) cr1v[6]: cmp is used in conjunction with tbprot, bp3, bp2, bp1 and bp0 bits to provide more flexibility for the array protection ma p, to protect from 1/2 to all of the array. lb[3:0] cr1v[5:2]: these bits are volatile copies of the related otp bits of cr1nv. these bits track any changes to the related otp version of these bits. quad data width (quad) cr1v[1] : when set to 1, this bit switches the data width of the device to 4 bit - quad mode. that is, wp# becomes io2 and io3 / reset# beco mes an active i/o signal when cs# is low or the reset# input when cs# is high. the wp# input is not monitored for its normal function and is internally set to high (inactive). the commands for serial, and dual i/o read still function normally but, there is no need to drive the wp# input for those command s when switching between commands using different data path widths. simi larly, there is no requirement to drive the io 3 / reset# during those commands (while cs# is lo w). the quad bit must be set to one when using the quad output read, quad i/o read, ddr quad i/o read. the volatile register write for qio mode has a short and well defined time (t qen ) to switch the device interface into qio mode and (t qex ) to switch the device back to spi mode. following commands can then be immediatel y sent in qio protocol. while qpi mode is entered or exited by the qpien and qpiex commands, or by setting the cr2v[3] bit to 1, the quad data width mode is in use whether the quad bit is set or not. status register protect 1(srp1) cr1v[0] : the srp1 bit, when set to 1, protects the current state of the sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv register s by preventing any write of these registers. see status register protect (srp1, srp0) on page 47 . as long as the srp1 bit remains cleared to logic 0 the sr1n v, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv, and dlrv registers are not protected by srp1. however, these regist ers may be protected by srp0 (sr1v[7]) and the wp# input. once the srp1 bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-on cycle or a hardw are reset. software reset will not affe ct the state of the srp1 bit. the cr1v[0] srp1 bit is volatile and the default state of srp1 after power-on comes fr om srp1_d in cr1nv[0 ]. the srp1 bit can be set in parallel with updating other values in cr1v by a single wrr or wrar command. table 13. configuration register 1 volatile (cr1v) bits field name function type default state description 7 sus suspend status volatile read only cr1nv 1 = erase / program suspended 0 = erase / program not suspended 6 cmp complement protection volatile 0 = normal protection map 1 = inverted protection map 5 lb3 volatile copy of security region lock bits volatile read only not user writable see cr1nv[5:2] otp lock bits 3:0 for security regions 3:0 0 = security region not locked 1 = security region permanently locked 4 lb2 3 lb1 2 lb0 1 quad quad i/o mode volatile 1 = quad 0 = dual or serial 0 srp1 status register protect 1 volatile lock current state of sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv 1 = registers locked 0 = registers un-locked document number: 002-00124 rev. *f page 34 of 158 s25fl256l/S25FL128L 6.6.4 configuration register 2 configuration register 2 controls certain interface functions. the register bits can be read and changed using the read any reg ister and write any register commands. the non-vola tile version of the register provides th e ability to set the por, hardware reset, or software reset state of the controls. the volatile version of the register controls the feat ure behavior during normal operatio n. 6.6.4.1 configuration register 2 non-volatile (cr2nv) related commands: non-volatile write e nable (wren 06h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). io3 _reset non-volatile cr2nv[7]: this bit controls the por, hardware reset, or software reset state of the io3 signal behavior. most legacy spi devices do not have a hardware reset input signal due to the limited signal count and connections available in traditional spi device packages. the fl-l fa mily provides the option to use the io3 signal as a hardware reset input when the i o3 signal is not in use for transferring info rmation between the host system and the memory. this non-vo latile io3_reset configura tion bit enables the device to start immediately (boot) with io3 enabled for use as a reset# signal. output impedance non- volatile cr2nv[6:5]: these bits control the por, hardware reset, or software reset state of the io signal output impedance (drive strength) . multiple drive strength are available to help match the output impedance with the system pri nted circuit board environment to minimize overshoot and ringing. t hese non-volatile output impedance configuration bits enable the device to start immediately (boot) with the appropriate drive strength. table 15. output impedance control table 14. configuration register 2 non-volatile (cr2nv) bits field name function type default state description 7 io3r_nv io3_reset non-volatile 0 1 = enabled -- io3_reset is used as io3 / reset# input when cs# is high or quad mode is disabled cr1v[1]=0 or qpi is disabled (cr3v[3] = 0) 0 = disabled -- io3 has no alternate function, hardware reset is disabled.provides the defau lt state for t he io3 / reset# function enable. 6 oi_nv output impedance 1 provides the default outp ut impedance state. see table 15, output impedance control on page 34 . 5 1 4 rfu reserved 0 reserved for future use 3 qpi_nv qpi 0 1 = enabled -- qpi (4-4-4) protocol in use 0 = disabled -- legacy spi protocols in use, instruction is always serial on si provides the default state for qpi mode. 2wps_nv write protect selection 0 provides the default state for wps 0 = legacy protection 1 = individual block lock 1adp_nv address length at power-up 0 provides the default state for address length 1 = 4 byte address 0 = 3 byte address 0 rfu reserved 0 reserved for future use cr2nv[6:5] impedance selection typical impedance to v ss (ohms) typical impedance to v cc (ohms) notes 00 18 21 01 26 28 10 47 45 11 71 64 factory default document number: 002-00124 rev. *f page 35 of 158 s25fl256l/S25FL128L qpi non-volatile cr2nv[3]: this bit controls the por, hardware reset, or soft ware reset state of the expected instruction width for all commands. legacy spi commands always send the instruction one bit wide (serial i/o) on the si (io0) signal. the fl-l family also supports the qpi mode in which all transfers between the host system and memory are 4 bits wide on io0 to io3, including a ll instructions. this non-volatile qp i configuration bit enables the device to start immediately (boot) in qpi mode rather than th e legacy serial instruction mode. the recommended procedure for moving to qpi mode is to first use the qpien (38h) command, the wrr or wrar command can also set cr2v[3]=1, qpi mode. the volatile re gister write for qpi mode has a short and well defined time (t qen ) to switch the device interface into qpi mode and (t qex ) to switch the device back to spi mode following commands can then be immediately sent in qpi protocol. the wrar command can be used to program cr2nv[3]=1, followed by polling of sr1v[0] to know when the programming operation is co mpleted. similarly, to exit qpi mode use the qpiex (f5h) command. the wrr or wrar command can also be used to clear cr2v[3]=0. write protect selection non-volatile cr2nv[2]: this bit controls the por, hardware rese t, or software reset state of the write protect method. this non-volatile configuration bit enables the device to start immediately (boot) with individual block lock protection rather than legacy block protection. address length at power-up non-volatile cr2nv[1]: this bit controls the por, hardware re set, or software reset state of the expected address length for all commands that require address and are not fixed 3 byte or 4 byte only address. most commands that need an address are legacy spi commands t hat traditionally used 3 byte (24 bit) add ress. for device densities greater than 128 mb a 4 byte (32 bit) address is required to access the entire memo ry array. the address length configuration bit is used to change all 3 byte address commands to expect 4 byte address. see table 40, fl-l family command set (sorted by function) on page 62 for command address length. this non-volatile address lengt h configuration bit enables t he device to start immediately (boot) in 4 byte address mode rather than the legacy 3 byte address mode. 6.6.4.2 configuration register 2 volatile (cr2v) related commands: read configuration regi ster 2 (rdcr2 15h), read any register (rdar 65h), write enable for volatile (wrenv 50h), write register (wrr 01h), write any register (wra r 71h), enter 4 byte address mode (4ben b7h), exit 4 byte address mode (4bex e9h), enter qpi (38h), exit qpi (f5h). this is the register displayed by the rdcr2 command. io3 reset cr2v[7]: this bit controls the io3 / reset# signal behavior. this volatile io3 reset configuration bit enables the use of io3 as a reset# input during normal operation when cs# is high or quad mode is disabled (cr1v[1] = 0) or qpi is disabled (cr3v[3] = 0). table 16. configuration register 2 volatile (cr2v) bits field name function type default state description 7 io3r io3_reset volatile cr2nv 1 = enabled -- io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=0 or qpi is disabled (cr3v[3] = 0). 0 = disabled -- io3 has no alte rnate function, hardware reset through io3 / reset# input is disabled. 6 oi output impedance see table 15, output impedance control on page 34 . 5 4 rfu reserved reserved for future use 3 qpi qpi 1 = enabled -- qpi (4-4-4) protocol in use 0 = disabled -- legacy spi protocols in use, instruction is always serial on si 2 wps write protect selection 0 = legacy block protection 1 = individual block lock 1adp address length at power-up volatile read only read status only bit 1 = 4 byte address 0 = 3 byte address 0 ads address length status volatile cr2nv[1] current address mode 1 = 4 byte address 0 = 3 byte address document number: 002-00124 rev. *f page 36 of 158 s25fl256l/S25FL128L output impedance cr2v[6:5]: these bits control the io signa l output impedance (drive strength). this volatile output impedance configuration bit enables the user to adjust the drive strength during normal operation. qpi cr2v[3]: this bit controls the expected instru ction width for all commands. this volatile qpi configuration bit enables the device to enter and exit qpi mode during normal operation. when this bit is set to qpi mode, the quad mode is active, independe nt of the setting of qio mode (cr1v[1]). when this bit is cleared to legacy spi mode, th e quad bit is not a ffected. the qpi cr2v[3 ] bit can also be set to ?1? by the qpien (38h) co mmand and set to ?0? by the qpiex (f5h) command. write protect selection cr2v[2]: this bit selects which array protection method is used; see legacy block protection on page 48 ) or individual block lock (ibl) protection on page 53 . these volatile configuration bits enabl e the user to change protection method during normal operation. address length at po wer-on (adp) cr2v[1]: this bit is read only and shows what t he address length will be after power-on reset, hardware reset, or software reset for all commands that require address and are not fixed 3 byte or 4 byte address. address length stat us (ads) cr2v[0]: this bit controls the expected address length for all commands that require address and are not fixed 3 byte or 4 byte address. see table 40, fl-l family command set (sorted by function) on page 62 for command address length. this volatile address length configuration bit enables the address length to be changed during normal operation . the four byte address mode (4ben) command directly sets this bit into 4 byte address mode and the (4bex) command exits sets this bit back into 3 byte address mode. this bit is also updat ed when the address length non-vo latile cr2nv[1] bit is updated. 6.6.5 configuration register 3 configuration register 3 controls the main flash array read commands burst wrap behavior and read latency. the burst wrap configuration does not affect commands readin g from areas other than the main flash arra y e.g. read commands for registers or security regions. the non-volatile version of the register provides the ability to se t the start up (boot) state of the control s as the contents are copied to the volatile version of the register du ring the por, hardware reset, or software re set. the volatile ver sion of the register controls the feature behavior during normal operation. the register bits can be read and changed using the, read co nfiguration 3 (rdcr3 33h), write registers (wrr 01h), read any register (rdar 65h), write any register (wra r 71h). the volatile version of the register can also be written by the set burst length (77h) command. 6.6.5.1 configuration register 3 non-volatile (cr3nv) related commands: non-volatile write e nable (wren 06h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). table 17. qpi and qio mode control bits qpi cr2v[3] quad cr1v[1] description 00 sio mode: single and dual read, wp#/io2 input is in use as wp# pin and io3 / reset# input is in use as reset# pin 01 qio mode: single, dual, and quad read, wp#/io2 input is in use as io2 and io3 / reset# input is in use as io3 or reset# pin 1x qpi mode: quad read, wp#/io2 input is in use as io2 and io3 / reset# input is in use as io3 or reset# pin document number: 002-00124 rev. *f page 37 of 158 s25fl256l/S25FL128L wrap length non-vo latile cr3nv[6:5]: these bits controls the por, hardware reset, or software reset state of the wrapped read length and alignment. wrap enable non-volatile cr3nv[4]: this bit controls the por, hardware reset, or software reset state of the wrap enable. the commands affected by wrap enable are: quad i/o read, qpi read, ddr quad i/o read and ddr qpi read. this configuration bit enables the device to start immediately (boot) in wrapped burst read mode rather than the legacy sequential read mode. read latency non-vo latile cr3nv[3:0]: these bits control the por, hardware reset, or software reset state of the read latency (dummy cycle) delay in all variable latency read commands. t he following read commands have a variable latency period between the end of address or mode and the beginning of read data returning to the host: the latency delay per clock frequency for the following commands are: one dummy cycl e for all clock frequency's. the default latency code of ?0? is one dummy cycle. ? data learning pattern read dlprd (1-1-1) or (4-4-4) ? irp read irprd (1-1-1) or (4-4-4)) ? protect register read prrd (1-1-1) or (4-4-4) ? password read passrd (1-1-1) or (4-4-4) the latency delay per clock frequency for the following commands are shown in table 19 and table 20 . the default latency code of ?0? is 8 dummy cycles. ? fast read fast_read (1-1-1) ? quad-o read qor, 4qor (1-1-4) ? dual-o read dor, 4dor (1-1-2) ? dual i/o read dior, 4dior (1-2-2) ? quad i/o read qior, 4qior (1-4-4) or (4-4-4) ? ddr quad i/o read ddrqior, 4ddrqior(1-4-4) ? security regions read secrr (1-1-1) or (4-4-4) ? read any register rdar (1-1-1) or (4-4-4) ? read serial flash discoverable para meters rsfdp (1-1-1) or (4-4-4) the non-volatile read latency configuration bits set the number of read latency (dummy cycles) in use so the device can start immediately (boot) with an appropriate read latency for the host system. table 6.15 configuration register 3 non-volatile (cr3nv) bits field name function type default state description 7 rfu reserved non-volatile 0 reserved for future use 6 wl_nv wrap length default 1 00 = 8-byte wrap 01 = 16 byte wrap 10 = 32 byte wrap 11 = 64 byte wrap 5 1 4 we_nv wrap enable default 1 0 = wrap enabled 1 = wrap disabled 3 rl_nv read latency default 1 0 to 15 latency (dummy) cycles following read address or continuous mode bits. 20 10 00 document number: 002-00124 rev. *f page 38 of 158 s25fl256l/S25FL128L . table 19. latency code (cycles) versus frequency latency code 0 read command maximum frequency (mhz) fast read (1-1-1) dual-o read (1-1-2) dual i/o read (1-2-2) quad-o read (1-1-4) quad i/o read (1-4-4) quad i/o read qpi (4-4-4) ddr quad i/o (1-4-4) qpi (4-4-4) mode cycles = 0 mode cycles = 0 mode cycles = 4 mode cycles = 0 mode cycles = 2 mode cycles = 2 mode cycles = 1 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 150 50 75 35 35 35 20 265 65 85 45 45 45 25 375 75 95 55 55 55 35 4 85 85 108 65 65 65 45 5 95 95 108 75 75 75 55 6 108 105 108 85 85 85 60 7 108 108 133 95 95 95 66 8 108 108 133 108 108 108 66 9 133 133 133 115 115 115 66 10 133 133 133 115 115 115 66 11 133 133 133 120 120 120 66 12 133 133 133 120 120 120 66 13 133 133 133 133 133 133 66 14 133 133 133 133 133 133 66 15 133 133 133 133 133 133 66 document number: 002-00124 rev. *f page 39 of 158 s25fl256l/S25FL128L notes: 1. sck frequency > 133 mhz sdr, or 66mhz ddr is not supported by this family of devices. 2. the dual i/o, quad i/o, qpi, ddr quad i/o, and ddr qpi command protocols include continuous read mode bits following the addr ess. the clock cycles for these bits are not counted as part of the latency cycles shown in th e table. example: the legacy quad i/o command has 2 continuous re ad mode cycles following the address. therefore, the legacy quad i/o command without additional read latency is supported only up to the frequency shown in the table for a read latency of 0 cycles. by increasing the variable read latency the frequency of the quad i/o command can be increased to allow operation up to the maximum supported 133 mhz frequency and qpi maximum supported 133 mhz. 3. other commands have fixed latency, e.g. r ead always has zero read latency, read un ique id has 32 dummy cycles and release fro m deep power-down has 24 dummy cycles. table 20. latency code (cycles) versus frequency latency code 0 read command maximum frequency (mhz) read any register (1-1-1) read any register qpi (4-4-4) security region read (1-1-1) security region read qpi (4-4-4) read sfdp rsfdp (1-1-1) read sfdp rsfdp qpi (4-4-4) mode cycles = 0 mode cycles = 0 mode cycles = 0 mode cycles = 0 mode cycles = 0 mode cycles = 0 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 dummy cycles = 8 1 501550155015 2 652565256525 3 753575357535 4 854585458545 5 955595559555 6 108 65 108 65 108 65 7 108 75 108 75 108 75 8 108 85 108 85 108 85 9 133 95 133 95 133 95 10 133 108 133 108 133 108 11 133 115 133 115 133 115 12 133 115 133 115 133 115 13 133 120 133 120 133 120 14 133 120 133 120 133 120 15 133 133 133 133 133 133 document number: 002-00124 rev. *f page 40 of 158 s25fl256l/S25FL128L 6.6.5.2 configuration register 3 volatile (cr3v) related commands: read configuration 3 ( rdcr3 33h), write enable for volatile (wrenv 50h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h), set bu rst length (sbl 77h). this is the register displayed by the rdcr3 command. wrap length cr3v[6:5]: these bits controls the wrapped read length and alignment during normal operation. these volatile configuration bits enable the user to adjust th e burst wrapped read length during normal operation. wrap enable cr3v[4]: this bit controls the burst wrap fe ature. this volatile configuration bi t enables the device to enter and exit burst wrapped read mode during normal operation. when cr3v[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed. when cr3v[4]=0, the wrap mode is enabled and a fixed length and al igned group of 8, 16, 32, or 64 bytes is read starting at the byte address provided by the read command and wrapping around at the group alignment boundary. read latency cr3v[3:0]: these bits set the read latency ( dummy cycle) delay in variable late ncy read commands. these volatile configuration bits enable the user to adjust the read latency during normal operation to optimiz e the latency for different com mands or, at different operating frequencies, as needed. 6.6.6 individual and region protection register (irp) related commands: irp read (irprd 2bh) and irp program (ir pp 2fh), read any register ( rdar 65h), write any register (wrar 71h). the irp register is a 16 bit otp memory location used to permanently configure the behavior of individual and region protection (irp) features. irp does not have user programm able volatile bits, all defined bits are otp. table 21. configuration register 3 volatile (cr3v) bits field name function type default state description 7 rfu reserved volatile cr3nv reserved for future use 6 wl wrap length 00 = 8-byte wrap 01 = 16 byte wrap 10 = 32 byte wrap 11 = 64 byte wrap 5 4 we wrap enable 0 = wrap enabled 1 = wrap disabled 3 rl read latency 0 to 15 latency (dummy) cycles following read address or continuous mode bits. 2 1 0 document number: 002-00124 rev. *f page 41 of 158 s25fl256l/S25FL128L the default state of the irp bits are programmed by cypress. security regions read password mode enable (secrrp) irp[6]: when programmed to ?0?, secrrp enables the security region 3 read password mode when pwdmlb bit irp[2] is program at same time or later. the secrrp bit can only be programmed when irp[2:0] = ?111?, if not prog ramming will fail with p_err set to 1. see section 7.7.4, security region read password protection on page 59 . ibl lock boot bit (ibllbb) irp[4]: the default state is 1, all individual ibl bits are set to ?0? in the protected state, following power-up, hardware reset, or software reset. in order to program or erase the array the global ibl unlock or the sector / block ibl unlock command must be given before the program or erase command s. when programmed to 0, all the individual ibl bits are in the un-protected state following power-up, hardware reset, or software reset. the ibllbb bit can only be programmed when irp[2:0] = ?111?, if not programming will fail with p_err set to ?1?. see section 7.6.2, individual block lock (ibl) protection on page 53 . password protection mode lock bit (pwdmlb) irp[2]: when programmed to ?0?, the passw ord protection mode is permanently selected to protect the security regions 2 and 3 and pointer regi on. the pwdmlb bit can only be programmed when irp[2:0] = ?111?, if not programming will fail with p_err set to 1. see section 7.7.3, password protection mode on page 58 . after the password protection mode is selected by programming irp[ 2] = ?0?, the state of all ir p bits are locked and permanentl y protected from further programming. attempting to program any irp bits will result in a programming error with p_err set to 1. the password must be programmed and verified, before the password mode (irp[2]=0) is set. power supply lock-down protection mode lock bit (pslmlb) irp[1]: when programmed to 0, the power supply lock-down protection mode is permanently selected. the pslmlb bit can only be programmed when irp[2:0] = ?111?, if not programming will fail with p_err set to ?1?. table 22. irp register (irp) bits field name function type default state description 15 to 7 rfu reserved otp all bits are 1 reserved for future use 6 secrrp security region 3 read password mode enable bit otp 1 0 = security region 3 read password mode selected 1 = security region 3 read password not selected irp[6] is programmable if irp[2:0]= ?111? 5 rfu reserved otp 1 reserved for future use 4 ibllbb ibl lock boot bit otp 1 0 = all individual ibl bits are set to ?1? at power-up in the unprotected state 1 = all individual ibl bits are set to ?0? at power-up in the protected state irp[4] is programmable if irp[2:0]= ?111? 3 rfu reserved otp 1 reserved for future use 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mo de permanently enabled. 1 = password protection mode not permanently enabled. irp[2] is programmable if irp[2:0]= ?111? 1 pslmlb power supply lock-down protection mode lock bit otp 1 0 = power supply lock-down protection mode permanently enabled. 1 = power supply lock-down protection mode not permanently enabled. irp[1] is programmable if this is enabled by irp[2:0]= ?111? 0 permlb permanent protection lock otp 1 0 = permanent protection mo de permanently enabled. 1 = permanent protection mo de not permanently enabled. irp[0] is programmable if irp[2:0]= ?111? document number: 002-00124 rev. *f page 42 of 158 s25fl256l/S25FL128L after the power supply lock-down protection mode is selected by programming irp[1] = 0?, the state of all irp bits are locked a nd permanently protected from further programmi ng. attempting to program any irp bits will result in a programming error with p_er r set to ?1?. see section 7.7.1, irp register on page 57 . permanent protection lock bit (permlb) irp[0]: when programmed to 0, the permanent protection lock bit permanently protects the pointer region and security regions 2 and 3, this bi t provides a simple way to permanently protect the pointer reg ion and security regions 2 and 3 without the us e of a password or the prl command. see section 7.7.1, irp register on page 57 . pwdmlb (irp[2]), pslmlb (irp[1]) and permlb (irp[0]) are mutually excl usive, only one may be programmed to zero. irp bits may only be programmed while irp[2:0] = ?111?. attempting to pr ogram irp bits when irp[2:0] is not = ?111? will result in a programming error with p_err set to ?1?. t he irp protection mode should be selected during system c onfiguration to ensure that a malicious program does not select an undesired protection mode at a later time. by locking all the protection configuration via the irp mode selection, later alteration of the protec tion methods by malicious programs is prevented. 6.6.7 password register (pass) related commands: password re ad (passrd e7h) and password program (passp e 8h), read any register (rdar 65h), write any register (wrar 71h). the pass register is a 64 bit otp me mory location used to permanently define a password for the individual and re gion protection (irp) feature. pass d oes not have user programmable volatile bits, all defined bits are otp. a volatile copy of pass is used to satisfy read latency requirement s but the volatile register is not user writable or further de scribed. the password can not be read or programmed after irp[2] is programmed to ?0?. see table 22, irp register (irp) on page 41 . 6.6.8 protection register (pr) related commands: protection register r ead (prrd a7h) protection register lock (prl a6h), read any register (rdar 65h). pr does not have separate user programmable non-volatile bits, all defined bits are volatile read only st atus. the default stat e of the rfu bits is set by hardware. there is no non-volatile version of the pr register. the nvlock bit is used to protect the se curity regions 2 and 3 and pointer region pr otection. when nvlock[0 ] = 0, the security regions 2 and 3 and pointer region protection can not be changed. note: 1. the command protection register lock (prl), sets the nvlock =?1?. table 23. password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64 bit password. the password is no longer readable after the password protection mode is selected by programming irp register bit 2 to zero. table 24. protection status register (pr) bits field name function type default state description 7 rfu reserved volatile read only 00h reserved for future use 6 secrrp security regions read password irp[6] 0 = security region 3 password protected from read when nvlock = 0 1 = security region 3 not password protected from read 5 rfu reserved 0 reserved for future use 4 rfu reserved 0 reserved for future use 3 rfu reserved 0 reserved for future use 2 rfu reserved 0 reserved for future use 1 rfu reserved 0 reserved for future use 0 nvlock protect non- volatile configuration irp[2] and irp[0] 0 = security regions 2 and 3 and pointer region write protected 1 = security regions 2 and 3 and pointer region may be written. 1 document number: 002-00124 rev. *f page 43 of 158 s25fl256l/S25FL128L 6.6.9 individual block lock access register (iblar) related commands: ibl read (iblrd 3dh or 4iblrd e0h), ibl lock (i bl 36h or 4ibl e1h), ibl unlock (iblul 39h or 4ibul e2h), global ibl lock (gbl 7eh), global ibl unlock (gbul 98h). iblar does not have user programmable non-volatile bits, all bits are a representation of the volatile bits in the ibl array. t he default state of the ibl array bits is set by hardware. there is no non-volatile version of the iblar register. note 1. see figure 25, individual block lock / pointer region protection control on page 53 . 2. the ibl bits maybe read by the iblrd and 4iblrd commands. 6.6.10 pointer region prot ection register (prpr) related commands: set pointer region (sprp fbh or 4sprp e3h) , read any register (rdar 65h), write any register (wrar 71h). prpr contains user programmable non-volatile bits. the default state of the prpr bits is set by hardware. there is no volatile version of the prpr register. see section 7.6.3, pointer region protection (prp) on page 54 for additional details. table 25. ibl access register (iblar) bits field name function type default state description 7 to 0 ibl read or write ibl for individual sectors / blocks volatile irp[4]=1 then 00h else ffh 00h = ibl for the sector / block addressed is set to ?0? by the ibl, 4ibl and gbl commands protecting that sector from program or erase operations. ffh = ibl for the sector / block addressed is cleared to ?1? by the ibul, 4ibul and gbul commands not protecting that sector from program or erase operations. table 26. prp register (prpr) bits field name function type default state description a31 to a25 rfu reserved non- volatile 11111111b reserved for future use a24 prpad prp address 1 pointer address a24 in s25fl256l rfu in S25FL128L, a23 to a16 ffh pointer address a23 to a16 a15 to a12 fh pointer address a15 to a12 a11 prpall prp protect all 1 0 = protect pointer region selected sectors 1 = protect all sectors a10 prpen prp enable 1 0 = enable pointer region protection 1 = disable pointer region protection a9 prptb prp top/ bottom 1 0 = pointer region protection starts from the top (high address) 1 = pointer region protection starts from the bottom (low address) a8 rfu reserved 1 reserved for future use a7 to a0 rfu reserved ffh reserved for future use document number: 002-00124 rev. *f page 44 of 158 s25fl256l/S25FL128L 6.6.11 ddr data learning registers related commands: program dlrnv (pdlrnv 43h), write dlrv (wdlrv 4ah), data learning pattern read (dlprd 41h), read any register (rdar 65h), write any register (wrar 71h). the data learning pattern (dlp) resides in an 8-bit non-volatile da ta learning register (dlrnv) as well as an 8-bit volatile da ta learning register (dlrv). when shipped from cypress, the dlrnv value is 00h. once programmed, the dlrnv cannot be reprogrammed or erased; a copy of the data pattern in the dlrnv wil l also be written to the dlrv. the dlrv can be written to at any time, but on hardware and software reset or power cycles the data pattern will revert back to what is in the dlrnv. during the learning phase described in the spi ddr modes, the dlp will come from the dlrv. each io will output the same dlp value for every clock edge. for example, if the dlp is 34h (or binary 00110100) then during the first clo ck edge all io?s will output 0; subsequently, the 2nd clock edge all i/o?s will output 0, the 3rd will output 1, etc. when the dlrv value is 00h, no preamb le data pattern is presented durin g the dummy phase in the ddr commands. table 27. non-volatile data learning register (dlrnv) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transfe rred to the host during ddr read com- mand latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. table 28. volatile data learning register (dlrv) bits field name function type default state description 7 to 0 vdlp volatile data learning pat- tern volatile takes the value of dlrnv during por or reset volatile copy of the nvdlp used to enable and deliver the data learn- ing pattern (dlp) to the outputs. the vdlp may be changed by the host during system operation. document number: 002-00124 rev. *f page 45 of 158 s25fl256l/S25FL128L 7. data protection 7.1 security regions the device has a 1024 byte address space that is separate from t he main flash array. this area is divided into 4, individually lockable, 256 byte length regions. see section 6.5, security regions address space on page 26 . the security region memory space is intend ed for increased system security. the data values can ?mate? a flash component with the system cpu/asic to prevent device substi tution. the security region address space is protected by the security region lock bits or the protection register nvlock bit (pr[0]). see section 7.1.4, security region lock bi ts (lb3, lb2, lb1, lb0) on page 45 . 7.1.1 reading security region memory regions the security region read command (secrr) uses the same protoc ol as fast read. read operations outside the valid 1024 byte security region address range wi ll yield indeterminate data. see section 8.7.3, security regions read (secrr 48h) on page 103 . security region 3 may be password protected from read by se tting the pwdmlb bit irp[2] = 0 and secrrp bit irp[6] = 0 when nvlock = 0. 7.1.2 programming the security regions the protocol of the security region programming co mmand (secrp) is the same as page program. see section 8.7.2, security region program (secrp 42h) on page 102 . the valid address range for security region program is depicted in table 6 on page 27 . security region program operations outside the valid security region address range will be ignored, without p_err in sr2v[5] set to ?1?. security regions 2 and 3 may be password protected fr om programming by setting the pwdmlb bit irp[2] = 0. 7.1.3 erasing the security regions the protocol of the security region erasing comm and (secre) is the same as sector erase. see section 8.7.1, security region erase (secre 44h) on page 102 . the valid address range for security region erase is depicted in table 6 on page 27 . security region erase operations outside the valid security region address range will be ignored, without e_err in sr2v set to ?1?. security regions 2 and 3 may be password protected fr om erasing by setting the pwdmlb bit irp[2] = 0. 7.1.4 security region lock bi ts (lb3, lb2, lb1, lb0) the security region lock bits (lb3, lb2, lb1, lb0) are non-vola tile one time program (otp) bi ts in configuration register 1(cr1nv[5:2]) that provide the write protect cont rol and status to the security regions. the default state of security regions 0 to 3 are unlocked. lb[3:0] can be set to 1 individually using the writ e status registers or write any register command. lb[3:0] are one time programmable (otp), once it?s set to 1, the corresponding 256 byte security region will become read-only permanently. 7.2 deep power down the deep power down (dpd) command offers an alternative means of data protection as all commands are ignored during the dpd state, except for the release from deep power down (res abh) command and hardware reset. thus, preventing any program or erase during the dpd state. document number: 002-00124 rev. *f page 46 of 158 s25fl256l/S25FL128L 7.3 write enable commands 7.3.1 write enable (wren) the write enable (wren) command must be written prior to an y command that modifies non-volatile data. the wren command sets the write enable latch (wel) bit. the wel bit is cleared to 0 (disables writes) during power-up, hardware and software res et, or after the devi ce completes the following commands: ?reset ? page program (pp or 4pp) ? quad page program (qpp or 4qpp) ? sector erase (se or 4se) ? half block erase (hbe or 4hbe) ? block erase (be or 4be) ? chip erase (ce) ? write disable (wrdi) ? write registers (wrr) ? write any register (wrar) ? security region erase (secre) ? security region byte programming (secrp) ? individual and region protec tion register program (irpp) ? password program (passp ) ? clear status register (clsr) ? set pointer region prot ection (sprp or 4sprp) ? program non-volatile data learning register (pdlrnv) ? write volatile data learning register (wdlrv) 7.3.2 write enable for vo latile registers (wrenv) the write enable volatile (wrenv) command must be written pr ior to write register (wrr) command that modifies volatile registers data. document number: 002-00124 rev. *f page 47 of 158 s25fl256l/S25FL128L 7.4 write protect signal when not in quad mode (cr1v[1] = 0) or qpi mode (cr2v[3] = 0), the wr ite protect (wp#) input in combination with the status register protect 0 (srp0) bit (sr1nv[7]) pr ovide hardware input signal controlled protection. when wp# is low and srp0 is set t o ?1? status register 1 (sr1nv and sr1v ), configuration register (cr1nv, cr1 v, cr2nv, cr2v, cr2nv and cr3nv) and ddr data learning registers (dlrnv and dlrv) ar e protected from alteration. this prevent s disabling or changing the protection defined by the legacy block protect bits or security region lock bits. see section 6.6.1, status register 1 on page 27 . 7.5 status register protect (srp1, srp0) the status register protect bits (srp1 and srp0) are volatile bits in the config uration and status regist ers (cr1v[0] and sr1v[ 7]). the srp bits control the met hod of write protection for sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv : software protection, hardware protection, or power supply lock-down notes: 1. srp0 is reloaded from srp0_nv (sr1nv[7]) default state after a power-down, power-up cycle, software or hardware reset. to ena ble hardware protection mode by the wp# pin at power-up set the srp0_nv bit to ?1?. 2. when srp1 = 1, a power-down, power-up cycle, or hardware reset, will change srp1 to 0 as srp1 is reloaded from srp1_d. 3. srp1_d can be written only when irp[2:0] =?111?. when srp1_d cr1nv[0]=?1? a power-down, power-up cycle, or hardware reset, will reload srp1 from srp1_d = ?1? the volatile bit srp1 is not writable, thus providing otp pr otection. when srp1_d is programmed to 1, recommended that srp0 _nv should also be programmed to 1 as an indication that otp protection is in use. 4. when qpi or qio mode is enabled (cr2v[3] or cr1v[1] = ?1?) t he internal wp# signal level is = 1 because the wp# external inpu t is used as io2 when either mode is active. this effectively turns off hard ware protection when srp1-srp0 = 01b. the register sr1nv, sr1v, cr1nv, cr1v, cr2nv, c r2v, cr3nv, dlrnv and dlrv are unlocked and can be written. 5. wip, wel, and sus (sr1[1:0] and cr1[7]) are volatile read only status bits that are never affected by the write status regist ers command. 6. the non-volatile version of sr1nv, cr1nv, cr2nv and cr3nv are not writable when protected by the srp bits and wp# as shown in the table. the non-volatile version of these status register bits are selected for writing when the write enable (06h) command precedes the write status re gisters (01h) command or the write any register (71h) command. 7. the volatile version of registers sr1v, cr1v and cr2v are not wr itable when protected by the sr p bits and wp# as shown in the table. the volatile version of these status register bits are selected for writing when the write en able for volatile status register (50h) command precedes the wri te status registers (01h) commandor the write enable (06h) command precedes the write any register (71h) command. 8. the volatile cr3v bits are not protected by the srp bits and may be written at any time by volatile (50h) write enable comman d preceding the write status registers (01h) command. the wrar (71h) and sbl (77h) commands are alternative ways to write bits in the cr3v register. 9. during system power up and boot code ex ecution: trusted boot c ode can determine whether t here is any need to change sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv values. if no changes are needed the srp1 bit (cr1v[0]) can be set to 1 to protect the sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv registers from changes during the remainder of normal system operation while power remains on. table 30. status register protection bits (high security) srp1_d cr1nv[0] srp1 cr1v[0] srp0 sr1v[7] wp# status register description 0 0 0 x software protection wp# pin has no control. sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv can be written. [factory default] 0 0 1 0 hardware protected when wp# pin is low sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are locked and can not be written. (1)(4) 0 0 1 1 hardware unprotected when wp# pin is high sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are unlocked and can be written. (1) 01xx power supply lock- down sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are protected and can no t be written to again until the next power-down, power-up cycle. (2) 1 1 x x one time program srp1_d cr1nv[0]= 1 sr1nv, sr1v, cr1nv, cr1v, cr2nv, cr2v, cr3nv, dlrnv and dlrv are permanently protected and can not be written. (3) document number: 002-00124 rev. *f page 48 of 158 s25fl256l/S25FL128L 7.6 array protection there are three types of memory array protection: legacy block (l bp), individual block lock (ibl) and pointer region (prp). the write protect selection (wps) bit is used by the user to enable one of two protecti on mechanisms: legacy block (lbp) protection (wps cr2v[2]=0)or individual block lock (ibl) protection (wps cr2v[2]=1). see configuration register 2 volatile (cr2v) on page 35 . only one protection mechanism can be enabled at one ti me. the legacy block protection is the default protection and is mutually exclusive with the ibl protection scheme. the pointe r region protection is enabled by the set pointer region protec tion command or the wrar command by the value of a10 = 0. see pointer region command on page 108 . when the pointer region protection is enabled it is logically ored with the legacy block protection or individual block lock protection. figure 24. wps selection of lb p or ibl and prp array protection 7.6.1 legacy block protection the legacy block protect bits (s25fl256l)status register bits bp3, bp2, bp1, bp0 -- sr1v[5:2]) (S25FL128L,) status register bits bp2, bp1, bp0 -- sr1v[4:2]) in co mbination with the configuration register tbprot (sr1v[6] s25fl256l) (sr1v[5] S25FL128L)bit, cmp (cr1v[6] bit and sec (s r1v[5] S25FL128L) can be used to protect an address range of the main flash array from program and erase operations. the size of the range is determi ned by the value of the bp bits and the upper or lower start ing point of the range is selected by the tbpr ot bit of the configuration register (sr1 v[6] s25fl256l ) (sr1v[5] S25FL128L,). the protection is complemented when the cmp bit (cr1v[6]) is set to 1. if the pointer region protection is enabled this region prot ection is logically ored with the legacy block protection region legacy block protection logic (address range compare) individual block protection logic (ibl bit array) mux or command address bp bits wps pointer region protection logic (address range compare) nvlock array location protected wps = 1 iblboot wps = 0 document number: 002-00124 rev. *f page 49 of 158 s25fl256l/S25FL128L table 31. S25FL128L block protection (cmp = 0) note: 1. x = don?t care. status register 128l (128mb) block protection (cmp=0) sec tbprot bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 none none none none 0 0 0 0 1 252 thru 255 fc0000h ? ffffffh 256 kb upper 1/64 0 0 0 1 0 248 thru 255 f80000h ? ffffffh 512 kb upper 1/32 0 0 0 1 1 240 thru 255 f00000h ? ffffffh 1 mb upper 1/16 0 0 1 0 0 224 thru 255 e00000h ? ffffffh 2 mb upper 1/8 0 0 1 0 1 192 thru 255 c00000h ? ffffffh 4 mb upper 1/4 0 0 1 1 0 128 thru 255 800000h ? ffffffh 8 mb upper 1/2 0 1 0 0 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/64 0 1 0 1 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/32 0 1 0 1 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/16 0 1 1 0 0 0 thru 31 000000h ? 1fffffh 2 mb lower 1/8 0 1 1 0 1 0 thru 63 000000h ? 3fffffh 4 mb lower 1/4 0 1 1 1 0 0 thru 127 000000h ? 7fffffh 8 mb lower 1/2 x x 1 1 1 0 thru 255 000000h ? ffffffh 16 mb all 1 0 0 0 1 255 fff000h ? ffffffh 4 kb upper 1/4096 1 0 0 1 0 255 ffe000h ? ffffffh 8 kb upper 1/2048 1 0 0 1 1 255 ffc000h ? ffffffh 16 kb upper 1/1024 1 0 1 0 x 255 ff8000h ? ffffffh 32 kb upper 1/512 1 0 1 1 0 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/4096 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/2048 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/1024 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/512 1 1 1 1 0 document number: 002-00124 rev. *f page 50 of 158 s25fl256l/S25FL128L table 32. S25FL128L (128mb) block protection (cmp = 1) notes 1. x = don?t care. . status register 128l legacy block protection (cmp=1) sec tbport bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 0 thru 255 000000h ? ffffffh 16 mb all 0 0 0 0 1 0 thru 251 000000h ? fbffffh 16,128 kb lower 63/64 0 0 0 1 0 0 thru 247 000000h ? f7ffffh 15,872 kb lower 31/32 0 0 0 1 1 0 thru 239 000000h ? efffffh 15 mb lower 15/16 0 0 1 0 0 0 thru 223 000000h ? dfffffh 14 mb lower 7/8 0 0 1 0 1 0 thru 191 000000h ? bfffffh 12 mb lower 3/4 0 0 1 1 0 0 thru 127 000000h ? 7fffffh 8 mb lower 1/2 0 1 0 0 1 4 thru 255 040000h ? ffffffh 16,128 kb upper 63/64 0 1 0 1 0 8 thru 255 080000h ? ffffffh 15,872 kb upper 31/32 0 1 0 1 1 16 thru 255 100000h ? ffffffh 15 mb upper 15/16 0 1 1 0 0 32 thru 255 200000h ? ffffffh 14 mb upper 7/8 0 1 1 0 1 64 thru 255 400000h ? ffffffh 12 mb upper 3/4 0 1 1 1 0 128 thru 255 800000h ? ffffffh 8 mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 255 000000h ? ffefffh 16,380 kb lower 4095/4096 1 0 0 1 0 0 thru 255 000000h ? ffdfffh 16,376 kb lower 2047/2048 1 0 0 1 1 0 thru 255 000000h ? ffbfffh 16,368 kb lower 1023/1024 1 0 1 0 x 0 thru 255 000000h ? ff7fffh 16,352 lower 511/512 1 0 1 1 0 1 1 0 0 1 0 thru 255 001000h ? ffffffh 16,380 kb upper 4095/4096 1 1 0 1 0 0 thru 255 002000h ? ffffffh 16,376 kb upper 2047/2048 1 1 0 1 1 0 thru 255 004000h ? ffffffh 16,368 kb upper 1023/1024 1 1 1 0 x 0 thru 255 008000h ? ffffffh 16,352 kb upper 511/512 1 1 1 1 0 document number: 002-00124 rev. *f page 51 of 158 s25fl256l/S25FL128L table 33. s25fl256l (256mb) upper array compleme nt legacy block protection (tbprot = 0, cmp = 1) status register content s25fl256l legacy block protection (tbprot =0, cmp =1) bp3 bp2 bp1 bp0 number protected blocks protected blocks protected density (kb) protected portion 0 0 0 0 512 0-511 32768 all 0 0 0 1 511 0-510 32704 lower 511/512 0 0 1 0 510 0-509 32640 lower 255/256 0 0 1 1 508 0-507 32512 lower 127/128 0 1 0 0 504 0-503 32256 lower 63/64 0 1 0 1 496 0-495 31744 lower 31/32 0 1 1 0 480 0-479 30720 lower 15/16 0 1 1 1 448 0-447 28672 lower 7/8 1 0 0 0 384 0-383 24576 lower 3/4 1 0 0 1 256 0-255 16384 lower 1/2 1010 0 none 0 none 1011 0 none 0 none 1100 0 none 0 none 1101 0 none 0 none 1110 0 none 0 none 1111 0 none 0 none table 34. s25fl256l (256mb) lower array complement legacy block protection (tbprot = 1, cmp = 1) status register content s25fl256l legacy block protection (tbprot =1, cmp =1) bp3 bp2 bp1 bp0 number protected blocks protected blocks protected density (kb) protected portion 0 0 0 0 512 0-511 32768 all 0 0 0 1 511 1-511 32704 upper 511/512 0 0 1 0 510 2-511 32640 upper 255/256 0 0 1 1 508 4-511 32512 upper 127/128 0 1 0 0 504 8-511 32256 upper 63/64 0 1 0 1 496 16-511 31744 upper 31/32 0 1 1 0 480 32-511 30720 upper 15/16 0 1 1 1 448 64-511 28672 upper 7/8 1 0 0 0 384 128-511 24576 upper 3/4 1 0 0 1 256 256-511 16384 upper 1/2 1010 0 none 0 none 1011 0 none 0 none 1100 0 none 0 none 1101 0 none 0 none 1110 0 none 0 none 1111 0 none 0 none document number: 002-00124 rev. *f page 52 of 158 s25fl256l/S25FL128L table 36. s25fl256l (256mb) lower array leg acy block protection (tbprot = 1, cmp = 0) table 35. s25fl256l (256mb) upper array legacy block protection (tbprot = 0, cmp = 0) status register content s25fl256l legacy block protection (tbprot =0, cmp =0) bp3 bp2 bp1 bp0 number protected blocks protected blocks protected density (kb) protected portion 0000 0 none 0 none 0 0 0 1 1 511 64 upper 1/512 0 0 1 0 2 510-511 128 upper 1/256 0 0 1 1 4 508-511 256 upper 1/128 0 1 0 0 8 504-511 512 upper 1/64 0 1 0 1 16 496-511 1024 upper 1/32 0 1 1 0 32 480-511 2048 upper 1/16 0 1 1 1 64 448-511 4096 upper 1/8 1 0 0 0 128 384-511 8192 upper 1/4 1 0 0 1 256 256-511 16384 upper 1/2 1 0 1 0 512 0-511 32768 all 1 0 1 1 512 0-511 32768 all 1 1 0 0 512 0-511 32768 all 1 1 0 1 512 0-511 32768 all 1 1 1 0 512 0-511 32768 all 1 1 1 1 512 0-511 32768 all status register content s25fl256l legacy block protection (tbprot =0, cmp =0) bp3 bp2 bp1 bp0 number protected blocks protected blocks protected density (kb) protected portion 0000 0 none 0 none 0 0 0 1 1 0 64 lower 1/512 0 0 1 0 2 0-1 128 lower 1/256 0 0 1 1 4 0-3 256 lower 1/128 0 1 0 0 8 0-7 512 lower 1/64 0 1 0 1 16 0-15 1024 lower 1/32 0 1 1 0 32 0-31 2048 lower 1/16 0 1 1 1 64 0-63 4096 lower 1/8 1 0 0 0 128 0-127 8192 lower 1/4 1 0 0 1 256 0-255 16384 lower 1/2 1 0 1 0 512 0-511 32768 all 1 0 1 1 512 0-511 32768 all 1 1 0 0 512 0-511 32768 all 1 1 0 1 512 0-511 32768 all 1 1 1 0 512 0-511 32768 all 1 1 1 1 512 0-511 32768 all document number: 002-00124 rev. *f page 53 of 158 s25fl256l/S25FL128L 7.6.2 individual block lock (ibl) protection individual block lock bits (ibl) are volatile, with one bit for each sector / block, and each bit can be individually modified. by issuing the ibl or gbl commands, a ibl bit is set to ?0? protecting each related sector / block. by issu ing the ibul or gul commands, a ibl bit is cleared to ?1? unprotecting each rela ted sector or block. by issuing the iblr d command the state of each ibl bit can be read. this feature allows software to easily pr otect individual sectors / blocks against i nadvertent changes, yet does not prevent th e easy removal of protection when changes are needed. the ibl?s can be set or cleared as often as needed as they are volatile bits. every main 64kb block and the 4kb sectors in bottom and top blocks has a volatile individual block lock bit (ibl) associated wi th it. when a sector / block ibl bit is ?0?, the related se ctor/block is protected from program and erase operations. if the pointer region protection is enabled this pr otected region is logica lly ored with the ibl bits. following power-up, hardware reset, or soft ware reset the default state [ibllbb = 1] (see table 22, irp register (irp) on page 41 ) all individual ibl bits are set to ?0? in the protected state. in order to program or erase the array the global ibl unlock or the sector / block ibl unlock command must be given bef ore the program or erase commands. when [ibllbb = 0], all the individual ibl bits are set to ?1? in the un-protected state following power-up, hardware reset, or software reset. figure 25. individual block lock / pointer region protection control notes; 1. the ?m? is the top 64kb block. 2. the ?n is the top 4kb sector. pointer region protection enabled a10 = ?0? individual block lock bits (ibl) array wps = ?1? sector n logical or flash memory array sector n sector n-15 sector n-15 logical or block m block m-1 ... ... ... block m-1 logical or block 1 block 1 logical or ... ... ... sector 15 sector 0 block 0 ... sector 15 logical or sector 0 logical or ... ... ... ... ... ... ... document number: 002-00124 rev. *f page 54 of 158 s25fl256l/S25FL128L 7.6.3 pointer region protection (prp) the pointer region protection is defined by a non-volatile addr ess pointer that selects any 4kb sector as the boundary between protected and unprotected regions in the me mory. this provides a protection scheme wit h individual sector granularity that rema ins in effect across power cycles and reset operations. prp settings can also be protected from modification until the next power c ycle, until a password is supplied, or can be permanently locked. prp c an be used in combination with either the legacy block protect ion or individual block lock protection methods. when enabled, prp protection is logically ored with the protection method selected by the wps bit (cr2v[2]) the set pointer region protection (sprp fbh or 4sprp e3h) command (see section 8.9 on page 108 ) or write any register (wrar 71h) command to write the prpr register (see section 8.3.15 on page 80 ) is used to enable or disable prp, and set the pointer value. the s25fl256l device must have 4 byte addressing enabled (cr2v[0] = 1) to set the pointer region protection register prpr (see section 6.6.10 on page 43 ) this insures that a24 and a25 are set correctly. after the set block/pointer protection command is given or write any register (wrar 71h) command to write the prpr register, the value of a10 enables or disables the pointer protection mechani sm. if a10 = 1, then the pointer protection region is disabl ed. this is the default state, and the rest of pointer values ar e don?t care. if a10=0, then the pointer protection region is enabl ed. the value of a10 is written in the non-volatile pointer bit in the prpr. the pointer address values for rfu bits are don?t care but these bit locations will read back as ones. see section 6.6.10 on page 43 for additional information on the prpr. if the pointer protection mechanism is enabled, the pointer valu e determines the block boundary between the protected and the unprotected regions in the memory . the pointer boundary is set by the three (a23 -a12) or four (a31-a12) address bytes written t o the non-volatile pointer value in the prpr. the area that is unp rotected will be inclusive of the 4kb sector selected by the po inter value. the value of a9 is used to determine whet her the region that is unprot ected will start from the top (highest address) or bottom (lowest address) of the memory array to the location of the pointe r. if a9=0 when the sprp or 4sprp command is issued followed by a the address, then the 4-kb sector whic h includes that address and all the sector s from the bottom up (zero to higher addre ss) will be unprotected. if a9=1 when the sprp or 4sprpcommand is issued followed by add ress then the 4-kb se ctor which includes that address and all the sectors from the t op down (max to lower address) will be unprot ected. the value of a9 is in the non-vo latile pointer value in the prpr. the a11 bit can be used to protect all sectors. if a11=1, then al l sectors are protected. if a11= 0, then the u nprotected range will be determined by amax-a12. the value of a11 is in the non-volatile pointer value in the prpr. the sprp or 4sprp command is ignored during a suspend oper ation because the pointer value cannot be erased and re- programmed during a suspend. the sprp or 4sprp command is ignored if nvlock pr[0]=0. the read any register 65h command (see section 8.3.14 on page 78 ) reads the contents of prp acce ss register. this allows the contents of the pointer to be read out for test and verification. table 37. prp table a11 a10 a9 protect address range unprotect address range comment x1 x none all a10 = 1 is prp disabled (this is the default state and the rest of pointer value is don't care). 00 0 1ffffff to (a[31:12]+1) a[31:12] to 0000000 the 4-kb sector which includes that addre ss and all the sectors from the bottom up (zero to higher address) will be unprotected. 00 1 (a[31;12]-1) to 0000000 1ffffff to a[31:12] the 4-kb sector which includes that addre ss and all the sectors from the top down (max to lower address) will be unprotected. 10 x 1ffffff to 000000 not applicable a10=0 and a11 =1 means protect all sectors and amax-a12 are don't care. document number: 002-00124 rev. *f page 55 of 158 s25fl256l/S25FL128L if the pointer protect scheme is active (a10=0), and the pointer protects any portion of the address space to which an erase command is applied, the erase command fails. for example, if the pointer protection is protecting 4kb of the array that would b e affected by a block erase command, that er ase command fails. chip erase ceh command is ignored if prp is enabled (a10=0) and this will set the e_err status bit. if the pointer region protection is enabled this protection is logically ored with either the legacy block protection region if wps cr2v[2]=0 or individual block lock protection if wps cr2v[2]=1 (see figure 24, wps selection of lbp or ibl and prp array protection on page 48 ). 7.7 individual and region protection individual and region protection (irp) is t he name used for a set of independent hardware and software methods used to disable or enable programming or erase operations on security regi ons 2 and 3 and the pointer region protection register. each method manages the state of the nvlo ck bit (pr[0]). when nvlock =1, the se curity regions 2 and 3 and the pointer region protection register (prpr) may be programmed and erased. when nvlock =0, the security regions 2 and 3 and prpr can not be programmed or erased. note, the security regions 2 and 3 are also protected respectively by lb2 or lb3=1 (cr1nv[4:5]). power supply lock-down protection is the def ault method. this method sets the nvlock bit to ?1? during por or hardware reset so that the nvlock related areas and registers are unprotected by a device reset. the prl (a6h) command clears the nvlock bit to ?0? to protect the nvlock related areas and registers. ther e is no command in the power supply lock-down method to set the nvlock bit to ?1?, therefore th e nvlock bit will remain at ?0? until the next power-off or hardware reset. the power supply loc k- down method allows boot code the option of changing security regions 2 and 3 or the value in prpr, by programming or erasing these non-volatile areas, then protecting these non-volatile areas from further chang e for the remainder of normal system opera tion by clearing the nvlock bit to ?0?. this is sometimes called boot-code controlled protection. the password method clears the protection register nvlock bit to 0 and sets the secrrp bit = irp[6] during por or hardware reset to protect the nvlock related areas and registers. the se crrp bit determines whether security region 3 is readable. a 64 bit password may be permanently programmed and hidden for the password method. the passu (eah) command can be used to provide a password for comparison with the hidden password. if the password matches, the nvlock bit is set to ?1? to unprotect the nvlock related areas and registers. the prl (a6h) command can be used to clear the nvlock bit to ?0? to turn on protection again. the permanent method permanently sets the secrrp bit = 1 and clears nvlock to 0. this permanently protects the security regions 2 and 3 and the prpr. the selection of the nvlock bit management method is made by programming otp bits in the irp register (irp[2 or 1 or 0] so as to permanently select the method used. an overview of all methods is shown in figure 26, permanent, password and power supply lock-down protection overview on page 56 . document number: 002-00124 rev. *f page 56 of 158 s25fl256l/S25FL128L figure 26. permanent, password and power supply lock-down protection overview power on reset or hardware reset password protection enabled irp[2]=0 security region 3 read password protection enabled irp[6]=0 power supply lock-down protection enabled irp[1]=0 nvlock = 0 security region 3 read & write locked security region 2 write locked pointer region protection write locked password unlock nvlock = 1 security regions 2 & 3 and pointer region protection are unlocked readable, erasable and programmable nvlock bit write no no yes yes nvlock = 0 security region 2 & 3 write locked pointer region protection write locked password unlock nvlock = 1 security regions 2 & 3 and pointer region protection are unlocked erasable and programmable nvlock bit write no no yes yes nvlock = 1 security regions 2 & 3 and pointer region protection are unlocked readable, erasable and programmable nvlock bit write nvlock = 0 security regions 2 & 3 write locked pointer region protection write locked no yes yes yes no default power lock protection irp register bits locked status register protect locked irp register bits locked status register protect locked irp register bits programmable status register protect otp option programmable read password protection mode protects security regions 3 from read, erase and programming, security region 2 and pointer region protection from erase and programming after powerup. a password unlock command will enable changes to security region 2 & 3 and pointer region protection. a nvlock bit write command turns the protection back on. password protection mode protects security regions 2 & 3 and pointer region protection from erase and programming after powerup. a password unlock command will enable changes to security region 2 & 3 and pointer region protection. a nvlock bit write command turns the protection back on. power supply lock-down protection mode does not protect security regions 2 & 3 and pointer region protection from erase and programming after powerup. the nvlock bit write command protects security regions 2 & 3 and pointer region protection until the next power off or reset. default mode does not protect security regions 2 & 3 and pointer region protection from erase and programming after powerup. the nvlock bit write command protects security regions 2 & 3 and pointer region protection until the next power off or reset. the otp option for status register protect is available to be programmed. permanent protection enabled irp[0]=0 irp register bits locked status register protect locked nvlock =0 permanent erase and program protection of security regions 2 & 3 and pointer region protection no no permanent protection mode permanently protects security regions 2 & 3 and pointer region protection from erase and programming note if security region lock bits lb 2 & 3 are protected cr1nv[5:4]=1, this overrides the nvlock and the security regions protected by the lb bits will be permanently protected from erase and programming. if read password is enabled security region 3 can still be read password protected. yes yes no nvlock = 1 security regions 2 & 3 and pointer region protection are unlocked readable, erasable and programmable nvlock bit write nvlock = 0 security regions 2 & 3 write locked pointer region protection write locked no yes document number: 002-00124 rev. *f page 57 of 158 s25fl256l/S25FL128L 7.7.1 irp register the irp register is used to permanently configure the behavio r of individual and region protection (irp) features. see table 22, irp register (irp) on page 41 . as shipped from the factory, all devices default to the powe r supply lock-down protection mode, with all regions unprotected. the device programmer or host system must then choose which protection method to use by progra mming one of t he, one-time programmable bits, permanent, po wer supply lock-down or password protection mode. programming one of these bits locks the part permanently in the selected mode: factory defaults irp register ? irp[6] = ?1? = read password protection mode not enabled. ? irp[4] = ?1? = ibl bits power-up in protected state. ? irp[2] = ?1? = password protection mode not enabled. ? irp[1] = ?1? = power supply lock-down protecti on mode not enabled but is the default mode. ? irp[0] = ?1? = permanent protection mode not enabled. irp register programming rules: ? if the read password mode is chosen, the secrrp bit must be programmed prior or at the same time as setting the password protection mode lock bits irp[2]. ? if the ibl bits power-up in unprotected mode is chosen, the ib llbb bit must be programmed prior or at the same time as setting one of the protection mode lock bits irp[2:0]. ? if the password mode is chosen, the pa ssword must be programmed prior to setting the password protection mode lock bits irp[2]. ? the protection modes are mutually exclusive, only one may be selected. once one of the protection modes is selected iprp[2:0], the irp register bits are pe rmanently protected from programming and no further changes to the otp register bits is allowed. if an attempt to change any of the register bits above, after the protection mode is selected, the operation will fail and p_err (sr2v[5]) will be set to 1. the programming time of the irp register is the same as the typical page programming time. t he system can determine the status of the irp register programming operation by re ading the wip bit in the status register. see section 6.6.1, status register 1 on page 27 for information on wip. see section 7.7.3, password protection mode on page 58 . 7.7.1.1 ibl lock boot bit the default ibl lock bit irp[4]=1, all the ibl bits on power-up or reset (after a hardware reset or software reset) to the ?pro tected state.? if the ibl lock bit irp[4]=0 (programmed), th e ibl power-up or reset to the ?unprotected state.? document number: 002-00124 rev. *f page 58 of 158 s25fl256l/S25FL128L 7.7.2 protection register (pr) 7.7.2.1 nvlock bit (pr[0]) the nvlock bit is a volatile bit for protecting: ? pointer region protection register ? security regions 2 and 3 when cleared to ?0?, nvlock locks the re lated regions. when se t to ?1?, it allows the rela ted regions to be changed. see section 6.6.8, protection register (pr) on page 42 for more information. the prl command is used to clear the nvlock bit to ?0?. the nvlock bit should be cleared to ?0? only after all the related regi ons are configured to the desired settings. in power supply lock-down protection mode, the nvlock is se t to ?1? during por or a hardware reset. a software reset command does not affect the nvlock bit. when clea red to ?0?, no software command sequence can set the nvlock bit to ?1?, only another hardware reset or power-up can set the nvlock bit. in the password protection mode, t he nvlock bit is cleared to ?0? during por, or a hardware reset. the nvlock bit can only be set to ?1? by the password unlock command. the permanent method permanently clears nvlock to 0. this pe rmanently protects the security regons 2 and 3 and the prpr. 7.7.2.2 security region read password lock bit (secrrp, pr[6]) the secrrp bit is a volatile bit for read protecting security r egion 3. when secrrp[6]=0 the security region 3 can not be read, see section 6.6.8, protection register (pr) on page 42 for more information. in the password protection mode, the secrrp bit is set equal to irp[6] during por or software or hardware reset. the nvlock bit can only be set to ?1? by the password unlock command. a software reset does not affect the nvlock bit. the permanent method permanently sets the secrrp bit = 1. this permanently leaves security region 3 readable. 7.7.3 password protection mode password protection mode allows an even higher level of security than the power supply lock-down protection mode, by requiring a 64-bit password for unlocking the nvlock bit. in addition to this password requirement, after power up, hardware reset, the nvlock bit is cleared to ?0? to ensure protection after power -up or reset. successful execution of the password unlock command by entering the entire password sets the nv lock bit to 1, allowing for sector nvlock related areas and registers modifications. password protection notes: ? once the password is programmed and verified, the password mode (irp[2]=0) must be set in order to prevent reading the password. ? the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in the cell left as a ?0? with no programming error set. ? the password is all ?1?s when shipped from cypress. it is located in its own memory space and is accessible through the use of the password program, password read, rdar, and wrar commands. ? all 64-bit password combinations are valid as a password. ? the password mode, once programmed, prevents reading t he 64-bit password and further password programming. all further program and read commands to the password region ar e disabled and these commands are ignored or return undefined data. there is no means to veri fy what the password is after the passw ord mode lock bit is selected. password verification is only allowed before selecting the password protection mode. ? the protection mode lock bits are not erasable. ? the exact password must be entered in order for the unlocking function to occur. if the password unlock command provided password does not match the hidden internal password, the unlo ck operation fails in the same manner as a programming operation on a protected sector. the p_err bit is set to one, the wip bit remains set, and the nvlock bit remains cleared to 0. document number: 002-00124 rev. *f page 59 of 158 s25fl256l/S25FL128L ? the password unlock command cannot be ac cepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run thro ugh all the 64-bit combinations in an attempt to correctly match a password. the read status register 1 command may be used to read the wip bit to determine when the device has completed the password unlock command or is ready to accept a new password command. when a valid password is provided the password unlock command does not insert th e 100 s delay before returning the wip bit to zero. ? if the password is lost after se lecting the password mode, there is no way to set the nvlock bit =1. 7.7.4 security region read password protection the security region read password protection enables protec ting security region 3 from read, program and erase. ? security region read password protection is an optional additi on to the password protection mode (described above). the security regions read password protection is e nabled when the user programs secrrp bit ?irp[6] = 0. the secrrp bit irp[6] must be programmed prior or at the same time as setting the password protection mode lock bits irp[2]. the security regions read password protection is not active until the password is programmed , irp[2] is programmed to 0. when the secrrp (pr[6]) bit is set to 0 the security region 3 is not readable. if these regions are read the resulting data is invalid and undefined. 7.7.5 recommended irp protection process during system manufacture, the flash device configurat ion should be defined by: 1. programming the security regions as desired. 2. set pointer region protection register as desired 3. program the password register (pass) if password prot ection will be used. 4. program the irp register as desired, including the sele ction of permanent, power supply lock-down or password irp protection mode in irp[2:0]. it is very important to explicitly select a protection mode so that later accidental or malicious programming of the irp register is prevented. this is to ensure that only the intended pr otection features are enabled. before or while programming the irp register: a. the ibllbb bit (irp[4]) may be used to cause all the ibl bits to power up in the unprotected state. b. the secrrp bit (irp[6]) may be programmed to select security regions read password protection to use the password to control read access to the security region 3. during system power up and boot code execution: if the power s upply lock-down protection mode is in use, trusted boot code can determine whether there is any need to modify the nvlock rela ted areas or registers. if no changes are needed the nvlock bit can be cleared to 0 via the prl command to protect the nvlock related areas or regist ers from changes during the remainder of normal system operation while power remains on. document number: 002-00124 rev. *f page 60 of 158 s25fl256l/S25FL128L 8. commands all communication between the host system and fl-l family me mory devices is in the form of units called commands. see section 5.2, command protocol on page 15 for details on command protocols. although host software in some cases is used to directly contro l the spi interface signals, the ha rdware interfaces of the host system and the memory device generally handle the details of signal relationships and timing. for this reason, signal relationships an d timing are not covered in detail within this software interface focused section of the document. instead, the focus is on the l ogical sequence of bits transferred in each command rather than the signal timing and relationships. following are some general signal relationship descriptions to keep in mind. for additional information on the bit level format and signal timing relationships o f commands, see section 5.2, command protocol on page 15 . ? the host always controls the chip select (cs#), serial clock (sck), and serial input (si) - si for single bit wide transfers. the memory drives serial output (so) for si ngle bit read transfers. the host and memory alternately drive the io0-io3 signals during dual and quad transfers. ? all commands begin with the host selecting the memory by driving cs# low before th e first rising edge of sck. cs# is kept low throughout a command and when cs# is returned high the command ends. generally, cs# remains low for eight bit transfer multiples to transfer byte granularity information. no commands will be accepted if cs# is returned high not at an 8 b it boundary. 8.1 command set summary 8.1.1 extended addressing to accommodate addressing abov e 128 mb, there are two options: 1. instructions that always require a 4-byte addr ess, used to access up to 32 gb of memory: table 38. extended address 4-byte address commands 2. a 4 byte address mode for backward compatibility to the 3 b yte address instructions. the standard 3 byte instructions can be used in conjunction with a 4 byte address mode contro lled by the address length conf iguration bit (cr2v[0]). the default value of cr2v[0] is loaded from cr2nv[1] (following power up, hardware reset, or software reset), to enable default 3-byte (24-bit) or 4 byte (32 bit) addressing. when the address length (cr2v[0]) set to 1, the legacy commands are changed to require 4-bytes (32-bits) for the address field. the following instructions can be used in conjunction with the 4 byte address mode configuration to switch from 3-bytes to 4-bytes of address field. command name function instruction (hex) 4read read 13 4fast_read read fast 0c 4dor dual output read 3c 4qor quad output read 6c 4dior dual i/o read bc 4qior quad i/o read ec 4ddrqior ddr quad i/o read ee 4pp page program 12 4qpp quad page program 34 4se sector erase 21 4hbe half block erase 53 4be block erase dc 4iblrd ibl read e0 4ibl ibl lock e1 4ibul ibl unlock e2 4sprp set pointer region protection e3 document number: 002-00124 rev. *f page 61 of 158 s25fl256l/S25FL128L table 39. extended address 4-byte address mode with 3-byte address commands command name function instruction (hex) rsfdp read sfdp 5a read read 03 fast_read read fast 0b dor dual output read 3b qor quad output read 6b dior dual i/o read bb qior quad i/o read eb ddrqior ddr quad i/o read) ed pp page program 02 qpp quad page program 32 se sector erase 20 hbe half block erase 52 be block erase d8 rdar read any register 65 wrar write any register 71 secre security region erase 44 secrp security region program 42 secrr security region read 48 iblrd ibl read 3d ibl ibl lock 36 ibul ibl unlock 39 sprp set pointer region protection fb document number: 002-00124 rev. *f page 62 of 158 s25fl256l/S25FL128L 8.1.2 command summary by function table 40. fl-l family command set (sorted by function) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi read device id rdid read id (jedec manufacturer id) 9f 108 0 yes rsfdp read jedec serial flash discoverable parameters 5a 133 3 or 4 yes rdqid read quad id af 108 0 yes ruid read unique id 4b 133 0 yes register access rdsr1 read status register 1 05 108 0 yes rdsr2 read status register 2 07 108 0 no rdcr1 read configuration register 1 35 108 0 no rdcr2 read configuration register 2 15 108 0 no rdcr3 read configuration register 3 33 108 0 no rdar read any register 65 133 3 or 4 yes wrr write register (status-1 and configuration-1,2,3) 01 133 0 yes wrdi write disable 04 133 0 yes wren write enable for non-volatile data change 06 133 0 yes wrenv write enable for volatile status and configuration registers 50 133 0 yes wrar write any register 71 133 3 or 4 yes clsr clear status register 30 133 0 yes 4ben enter 4 byte address mode b7 133 0 yes 4bex exit 4 byte address mode e9 133 0 yes sbl set burst length 77 133 0 yes qpien enter qpi 38 133 0 no qpiex exit qpi f5 133 0 yes dlprd data learning pattern read 41 133 0 yes pdlrnv program nv data learning register 43 133 0 yes wdlrv write volatile data learning register 4a 133 0 yes document number: 002-00124 rev. *f page 63 of 158 s25fl256l/S25FL128L read flash array read read 03 50 3 or 4 no 4read read 13 50 4 no fast_read fast read 0b 133 3 or 4 no 4fast_read fast read 0c 133 4 no dor dual output read 3b 133 3 or 4 no 4dor dual output read 3c 133 4 no qor quad output read 6b 133 3 or 4 no 4qor quad output read 6c 133 4 no dior dual i/o read bb 133 3 or 4 no 4dior dual i/o read bc 133 4 no qior quad i/o read (cr1v[1]=1) or cr2v[3]=1 eb 133 3 or 4 yes 4qior quad i/o read (cr1v[1]=1) or cr2v[3]=1 ec 133 4 yes ddrqior ddr quad i/o read (cr1v[1]=1 or cr2v[3]=1) ed 66 3 or 4 yes 4ddrqior ddr quad i/o read (cr1v[1]=1 or cr2v[3]=1) ee 66 4 yes program flash array pp page program 02 133 3 or 4 yes 4pp page program 12 133 4 yes qpp quad page program 32 133 3 or 4 no 4qpp quad page program 34 133 4 no erase flash array se sector erase 20 133 3 or 4 yes 4se sector erase 21 133 4 yes hbe half block erase 52 133 3 or 4 yes 4hbe half block erase 53 133 4 yes be block erase d8 133 3 or 4 yes 4be block erase dc 133 4 yes ce chip erase 60 133 0 yes ce chip erase (alternate instruction) c7 133 0 yes erase / program suspend / resume eps erase / program suspend 75 133 0 yes epr erase / program resume 7a 133 0 yes security region array secre security region erase 44 133 3 or 4 yes secrp security region program 42 133 3 or 4 yes secrr security region read 48 133 3 or 4 yes table 40. fl-l family command se t (sorted by func tion) (continued) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi document number: 002-00124 rev. *f page 64 of 158 s25fl256l/S25FL128L notes 1. commands not supported in qpi mode have undefined behavior if sent when the device is in qpi mode. 2. for s25fl256l device, the sprp command must be in 4 byte address mode with cr2v[0]=1. array protection iblrd ibl read 3d 133 3 or 4 yes 4iblrd ibl read e0 133 4 yes ibl ibl lock 36 133 3 or 4 yes 4ibl ibl lock e1 133 4 yes ibul ibl unlock 39 133 3 or 4 yes 4ibul ibl unlock e2 133 4 yes gbl global ibl lock 7e 133 0 yes gbul global ibl unlock 98 133 0 yes sprp set pointer region protection fb 133 3 or 4 (2) yes 4sprp set pointer region protection e3 133 4 yes individual and region protection irprd irp register read 2b 133 0 yes irpp irp register program 2f 133 0 yes prrd protection register read a7 133 0 yes prl protection register lock (n vlock bit write) a6 133 0 yes passrd password read e7 133 0 yes passp password program e8 133 0 yes passu password unlock ea 133 0 yes reset rsten software reset enable 66 133 0 yes rst software reset 99 133 0 yes mbr mode bit reset ff 133 0 yes deep power down dpd deep power down b9 133 0 yes res release from deep power down / device id ab 133 0 yes rfu reserved-18 reserved 18 rfu reserved-41 reserved 41 rfu reserved-43 reserved 43 rfu reserved-4a reserved 4a rfu reserved-ed reserved ed rfu reserved-ee reserved ee table 40. fl-l family command se t (sorted by func tion) (continued) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi document number: 002-00124 rev. *f page 65 of 158 s25fl256l/S25FL128L 8.1.3 read device identification there are multiple commands to read information about the device manufacturer, device type, and device features. spi memories from different vendors have used different commands and formats for reading information about the memories. the fl-l family supports the three device information commands. 8.1.4 register read or write there are multiple registers for reporting embedded operation st atus or controlling device c onfiguration options. there are commands for reading or writing these registers. registers contai n both volatile and non-volatile bits. non-volatile bits in re gisters are automatically erased and programmed as a single (write) operation. 8.1.4.1 monitoring operation status the host system can determine when a write, pr ogram, erase, suspend or ot her embedded o peration is complete by monitoring the write in progress (wip) bit in the status register. the read from status register 1 command or read any register command provides the state of the wip bit. the read from status register 2 or read any re gister command provid es the state of the program error (p_err) and erase error (e_err) bits in the status register indicate whether the most recent program or erase command has not completed successfully. when p_err or e_err bits are set to one, the wip bit will remain set to one indicating the device remains busy and unable to receive most new operat ion commands. only status reads (rdsr1 05h, rdsr2 07h), read any register (rdar 65h), read configuration rdcr1 and rdcr3, status clear (clsr 30h), and software reset (rsten 66h followed by rst 99h) are valid commands when p_err or e_err is set to 1. a clear status register (clsr) command must be sent to return the device to standby state. alternatively, hardwa re reset, or software reset (rsten 66h followed by rst 99h) ma y be used to return the device to standby state. 8.1.4.2 configuration there are commands to read, write, and prot ect registers that control interface path width, interface timing, interface address length, and some aspects of data protection. 8.1.5 read flash array data may be read from the memory starting at any byte boundary. data bytes are sequ entially read from incrementally higher byte addresses until the host ends the data transfer by driving cs# i nput high. if the byte address reaches the maximum address of t he memory array, the read will continue at address zero of the array. burst wrap read can be enabled by the set burst length ( sbl 77h) command with the requested wrapped read length and alignment, see section 8.3.16, set burst length (sbl 77h) on page 81 . burst wrap read is only for quad i/o and qpi modes there are several different read commands to specify different access latency and data path widths. double data rate (ddr) commands also define the address and data bit relationship to both sck edges: ? the read command provides a single address bit per sck ri sing edge on the si/io0 signal with read data returning a single bit per sck falling edge on the so/io1 signal. this command has zero latency between the address and the returning data but is limited to a maximum sck rate of 50mhz. ? other read commands have a latency period between the ad dress and returning data but can operate at higher sck frequencies. the latency depends on a conf iguration register read latency value. ? the fast read command provides a single address bit per sck rising edge on the si/io0 signal with read data returning a single bit per sck falling edge on the so/io1 signal. ? dual or quad output read commands provide address on si/io0 pin on the sck rising edge with read data returning two bits, or four bits of data per sck falling edge on the io0 - io3 signals. ? dual or quad i/o read commands provide address two bits or fo ur bits per sck rising edge with read data returning two bits, or four bits of data per sck falling edge on the io0 - io 3 signals. continuous read featur e is enabled if the mode bits value is axh. ? quad double data rate read commands provide address four bi ts per every sck edge with read data returning four bits of data per every sck edge on the io0 - io3 signals. continuous read feature is enabled if th e mode bits value is axh. document number: 002-00124 rev. *f page 66 of 158 s25fl256l/S25FL128L 8.1.6 program flash array programming data requires two commands: write enable (wren) , and page program (pp, 4pp, qpp, 4qpp). the page program command accepts from 1 byte up to 256 consecutive bytes of data (page) to be programmed in one operation. programming means that bits can either be left at 1, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 8.1.7 erase flash array the sector erase, half block eras e, block erase, or chip erase commands set all the bits in a sector or the entire memory array to 1. a bit needs to be first erased to 1 before programming can change it to a 0. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide, hal f block-wide, block-wide or array- wide (chip) level. the write en able (wren) command must precede an erase command. 8.1.8 security regions, legacy block pr otection, and indi vidual and region protection there are commands to read and program a separate one time pr otection (otp) array for permanent ly protected data such as a serial number. there are commands to contro l a contiguous group (block) of flash memo ry array sectors that are protected from program and erase operations.there are commands to control whic h individual flash memory arra y sectors are protected from program and erase operations. there is a mode to limit read access of security region 3 until a password is supplied. 8.1.9 reset there are commands to reset to the default conditions present a fter power on to the device. however, the software reset command s do not affect the current state of the srp1 or nvlock bits. in all other respects a software reset is the same as a hardware re set. there is a command to reset (exit from) the continuous read mode. 8.1.10 reserved some instructions are reserved for future use. in this generatio n of the fl-l family some of these command instructions may be unused and not affect dev ice operation, some may have undefined results. some commands are reserved to ensure that a legacy or alternate source device command is allowed without effect. this allows legacy software to issue some commands that are not relevant for the current generation fl-l family with the assurance these commands do not cause some unexpected action. some commands are reserved for use in special versions of the fl -l not addressed by this document or for a future generation. this allows new host memory controller designs to plan the fl exibility to issue these command instructions. the command format is defined if known at the time this document revision is published. document number: 002-00124 rev. *f page 67 of 158 s25fl256l/S25FL128L 8.2 identification commands 8.2.1 read identifi cation (rdid 9fh) the read identification (rdid) command provides read access to manufacturer identification, device identification. the manufacturer identification is assigne d by jedec. the device identificat ion values are assigned by cypress. any rdid command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress. the rdid instruction is shifted on si / io0. after the last bit of the rdid instruction is shifted into the device, a byte of m anufacturer identification, two bytes of device identification, will be shi fted sequentially out on so / io1, as a whole this information i s referred to as id. see section 10.2, device id address map on page 127 for the detail description of the id contents. continued shifting of output beyond the end of the defined id address spac e will provide undefined data. the rdid command sequence is terminated by driving cs# to the logic high state anytime during data output. the rdid command is supported up to 108 mhz. figure 27. read identification (rdid) command sequence this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3. figure 28. read identification (rdid) qpi mode command 8.2.2 read quad identification (rdqid afh) the read quad identification (rdqid) command provides read access to manufacturer ident ification, device identification. this command is an alternate way of reading the same information pr ovided by the rdid command while in qpi mode. in all other respects the command behaves the same as the rdid command. the command is recognized only when the device is in qpi mode (cr2v[3]=1) or quad mode ( cr1v[1]=1). the instruction is shifted in on io0-io3 for qpi mode and io0 fo r quad mode. after the last bit of the in struction is shifted into the device, a b yte of manufacturer identification , two bytes of device id entification will be shifted sequentially out on io0-io3. as a whole this in formation is referred to as id. see section 10.2, device id address map on page 127 for the detail description of the id contents. continued shifting of output beyond the en d of the defined id address space will prov ide undefined data. the command sequence i s terminated by driving cs# to the logic high state anytime during data output. cs# sck si_ io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruction d1 d2 d3 d4 data n document number: 002-00124 rev. *f page 68 of 158 s25fl256l/S25FL128L figure 29. read quad identification (rdqid) command sequence qpi mode figure 30. read quad identification (rdqid) command sequence quad mode 8.2.3 read serial flash discover able parameters (rsfdp 5ah) the command is initiated by shifting on si the instruction code ?5ah?, followed by a 24-bit (3 byte) address or 32-bit (4 byte) address (depending on the current address length configuration of cr 2v[0]), followed by the number of read latency (dummy cycles) set b y the variable read latency co nfiguration in cr3v[3:0]. the sfdp bytes are then shifted out on so/io1 starting at the fa lling edge of sck after the dummy cycles. the sfdp bytes are always shifted out with the msb first. if the 24-bit (3 byte) address or 32-bit (4 byte) address is set to any non-zero value, the selected location in the sfdp space is the starting point of th e data read. this enables random access to any parameter in the sfdp space. in spi mode the rsfdp command is supported up to 133 mhz. the variable read latency should be set to 8 cycles for co mpliance with the jedec jesd216 sf dp standard. th e non-volatile default variable read laten cy in cr3nv is set to 8 dummy cycles when the device is shipped from cypre ss. however, because the rsfdp command uses the same implementation as other variable address length and latency read commands, users are free to modify the address length and latency of the command if desired. continuous (sequential) read is s upported with the read sfdp command. figure 31. rsfdp command sequence note: a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command 13h. this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3. cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruction d1 d2 d3 d4 data n cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 instruction d1 data n cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 document number: 002-00124 rev. *f page 69 of 158 s25fl256l/S25FL128L figure 32. rsfdp qpi mode command sequence 8.2.4 read unique id (ruid 4bh) the read identification (ruid) co mmand provides read access to factory set read only 64 bit number that is unique to each devic e. the ruid instruction is shifted on si followed by four dummy byte s or 16 dummy bytes qpi (32 cl ock cycles). this latency period (i.e., dummy bytes) allows the device?s internal circuitry enough time to access data at the initial address. during latency cy cles, the data value on io0-io3 are ?don?t care? and may be high impedance. then the 8 bytes of unique id will be shifted sequentially out on so / io1. continued shifting of output bey ond the end of the defined unique id addre ss space will provide undefined data. the ruid command sequence is terminated by driving cs# to the logic high state anytime during data output. figure 33. read unique id (ruid) command sequence this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3. figure 34. read unique id (ruid) qpi mode command cs# sclk io0 io1 io2 io3 phase 4 0 20 4 0 4 0 4 0 4 0 4 0 5 1 21 5 1 5 1 5 1 5 1 5 1 6 2 22 6 2 6 2 6 2 6 2 6 2 7 3 23 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4 cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 63 62 61 60 59 58 57 56 55 5 4 3 2 1 0 instruction dummy byte 1 dummy byte 4 64 bit unique serial number cs# sclk io0 io1 io2 io3 phase 4 0 60 56 4 8 4 0 5 1 61 57 5 9 5 1 6 2 62 58 6 10 6 2 7 3 63 59 7 11 7 3 instruction dummy 1 dummy 2 dummy 3 dummy 13 dummy 14 dummy 15 dummy 16 64 bit unique serial number document number: 002-00124 rev. *f page 70 of 158 s25fl256l/S25FL128L 8.3 register access commands 8.3.1 read status regi ster 1 (rdsr1 05h) the read status register 1 (rdsr1) command allows th e status register 1 content s to be read from so/io1. the volatile version of status register 1 (sr1v) contents may be read at any time, even while a program, erase, or write operat ion is in progress. it is possible to read status register 1 contin uously by providing multiples of eight clock cycles. the status is updated for each eight cycle read. figure 35. read status register 1 (rdsr1) command sequence this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3. in qpi mode the read status register can be supported up to 108mhz clo ck frequency. to read status register 1 above 108mhz use the read any register command, see section 8.3.14, read any register (rdar 65h) on page 78 . figure 36. read status regi ster 1 (rdsr1) qpi mode command 8.3.2 read status regi ster 2 (rdsr2 07h) the read status register 2 (rdsr2) command allows th e status register 2 content s to be read from so/io1. the volatile status register 2 sr2v contents may be read at any time, even while a program, eras e, or write operation is in progress. it is possible to read the stat us register 2 continuously by providing mu ltiples of eight clock cycles. the status is updated for each eight cycle read. figure 37. read status register 2 (rdsr2) command in qpi mode, status register 2 may be r ead via the read any register command, see section 8.3.14, read any register (rdar 65h) on page 78. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 instruct. status updated status updated status cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status document number: 002-00124 rev. *f page 71 of 158 s25fl256l/S25FL128L 8.3.3 read configuration registers ( rdcr1 35h) (rdcr2 15h) (rdcr3 33h) the read configuration register (rdcr1, rdcr2, rdcr3) commands a llows the volatile configuration registers (cr1v, cr2v, cr3v) contents to be read from so/io1. it is possible to read cr1v, cr2v and cr3v continuously by prov iding multiples of eight clock cycles. the configuration registe rs contents may be read at any time, even while a program, erase, or write operation is in progress. to read the configuration reg ister 1, 2 and 3 at higher frequencies use the read any register command, see section 8.3.14, read any register (rdar 65h) on page 78 . figure 38. read configur ation register (rdcr1) (rdcr2) (rdcr3) command sequence in qpi mode, configuration register 1, 2 and 3 may be read via the read any register command, see section 8.3.14, read any register (rdar 65h) on page 78. 8.3.4 write registers (wrr 01h) the write registers (wrr) command allows new values to be wr itten to the status register 1, configuration register 1, configuration register 2 and c onfiguration register 3. before the write registers (wrr) command can be accepted by the device, a write enable (wren) or write enable for volatile register s (wrenv) command must be received. after the write enable (wren) command has been decoded successfully , the device will set the write enable lat ch (wel) in the status register to enable non-volatile write operations and di rect the values in the following wrr comm and to the non-volatile sr1nv, cr1nv, cr2nv and cr3nv registers. after the write enable for volatile registers (wrenv) command has been decoded successfully, the device directs the values in the following wrr command to the volatile sr1v, cr1v, cr2v and crv3 registers. the write registers (wrr) command is entered by shifting the inst ruction and the data bytes on si/io0. the status register is o ne data byte in length. a wrr operation directed to non-volatile registers by a preceding wren command, first erases non-volatile registers then programs the new value as a single operation, then copies the new non-volatile values to the volatile version of the registers. a wrr operation directed to volatile registers by a preceding wrenv command, updates the vo latile registers without affecting the rel ated non-volatile register values. the write re gisters (wrr) command will set the p_err or e_ err bits if there is a failure in the w rr operation. see section 6.6.2, status register 2 volatile (sr2v) on page 31 for a description of the error bits. the device hangs busy until clear status register (clsr) is used to clear the error and wip for return to standby. an y status or configuration regist er bit reserved for the future must be written as a ?0?. cs# must be driven to the logic high state after the eighth, sixteenth, twenty-fourth, or thirty-second bit of data has been la tched. if not, the write registers (wrr) command is not executed. if cs# is driven high after the: ? eighth cycle then only the status regist er 1 is written ? sixteenth cycle both the st atus 1 and configur ation 1 register s are written; ? twenty-fourth cycle status 1 and confi guration 1 and 2 registers are written; ? thirty-second cycle status 1 and configuration 1, 2 a nd 3 registers are written. as soon as cs# is driven to the logic hi gh state, the self-tim ed write registers (wrr) operation is initiated. while the write registers (wrr) operation is in progress, t he status register may still be read to c heck the value of the write-in progress (wi p) bit. the write-in progress (wip) bit is a ?1? during the self-timed wr ite registers (wrr) operation, a nd is a ?0? when it is complet ed. when the write registers (wrr) operat ion is completed, the write enable latch (wel) is set to a ?0?. the wrr command is protected from a hardware and software rese t, the hardware reset and software reset command are ignored and have no effect on the execution of the wrr command. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read document number: 002-00124 rev. *f page 72 of 158 s25fl256l/S25FL128L figure 39. write registers (wrr) command sequence this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3. figure 40. write register (wrr) command sequence qpi mode the write registers (wrr) command allows th e user to change the values of the legacy block protection bits in either the non- volatile status register 1 or in the volatile status register 1, to define the size of the area that is to be treated as read-onl y. the write registers (wrr) command also allows the user to set the status register prot ect 0 (srp0) bit to a ?1? or a ?0?. the status register protect 0 (s rp0) bit and write protect (wp#) signal allow the bp bits to be hardware protected. when the status register protect 0 (srp0 sr1v [7]) bit is a ?0?, it is possible to writ e to the status regist er provided that th e wren or wrenv command has previously been sent, regardless of whether wr ite protect (wp#) signal is driv en to the logic high or logi c low state. when the status register protec t 0 (srp0) bit is set to a ?1?, two cases need to be considered, depending on the state of write protect (wp#): ? if write protect (wp#) signal is driven to the logic high state, it is possible to write to the status and configuration regist ers provided that the wren or wrenv command ha s previously been sent before the wrr command. ? if write protect (wp#) signal is driven to the logic low state, it is not possible to write to the status and configuration registers even if the wren or wrenv command has previous ly been sent before the wrr command. attempts to write to the status and configuration registers are rejected, not acc epted for execution, and no error indication is provided. as a consequence, all the data bytes in the memo ry area that are protected by the legacy block protection bits of the status register, are also hardware protected by wp#. the wp# hardware protection can be provided: ? by setting the status register protect 0 (srp0) bit after driving write protect (wp#) signal to the logic low state; ? or by driving write protect (wp#) signal to the logic low state after setting the status register protect 0 (srp0) bit to a ?1? . the only way to release the hardware protec tion is to pull the write protect (wp#) sig nal to the logic high state. if wp# is permanently tied high, hardware protection of the bp bits can never be activated. hardware protection is disabled when quad mode is enabled (cr1 v[1] = 1) or qpi mode is enabled (cr2v[3] =1) because wp# becomes io2; therefore, it cannot be utilized. see section 7.5, status register protect (srp1, srp0) on page 47 for a table showing the srp and wp# control of status and configuration protection. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 input conf register-1 input conf register-2 input conf register-3 cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 instruct. input status 1 input config 1 input config 2 input config 3 document number: 002-00124 rev. *f page 73 of 158 s25fl256l/S25FL128L 8.3.5 write enable (wren 06h) the write enable (wren) command sets the write enable latch (wel ) bit of the status register 1 (sr1v[1]) to a ?1?. the write enable latch (wel) bit must be set to a ?1? by issuing the write enable (wren) command to enable write, program and erase commands. cs# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on si/io0. withou t cs# being driven to the logic high state after the eighth bit of the instruction byte has been latch ed in on si/io0, the write enab le operation will not be executed. figure 41. write enable (wren) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 42. write enable (wren) command sequence qpi mode 8.3.6 write disable (wrdi 04h) the write disable (wrdi) command clears the write enable latc h (wel) bit of the status register 1 (sr1v[1]) to a ?0?. the write enable latch (wel) bit may be cleared to a ?0? by i ssuing the write disable (wrdi) command to disable page program (pp, 4pp, qpp, 4qpp), sector erase (se), half block erase (hbe) , block erase (be), chip erase (ce), write registers (wrr or wrar), security region erase (secre), security region program (secrp), and other commands, t hat require wel be set to ?1? for execution. the wrdi command can be used by the user to pr otect memory areas against inadvertent writes that can possibly corrupt the contents of the memory. the wrdi command is ignored during an embedded operation while wip bit =1. cs# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on si/io0. withou t cs# being driven to the logic high state after the eighth bit of the instruction byte has been latch ed in on si/io0, the write disa ble operation will not be executed. figure 43. write disable (wrdi) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction document number: 002-00124 rev. *f page 74 of 158 s25fl256l/S25FL128L figure 44. write disable (w rdi) command sequence qpi mode 8.3.7 write enable for vola tile registers (wrenv 50h) the volatile sr1v, cr1v, cr2v and cr3v registers described in section 6.6, registers on page 27 , can be written by sending the wrenv command followed by the wrr command. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-vola tile bit write cycles or affect ing the endurance of the stat us or configuration non-volatile register bits. the wrenv command will not set the write enable latch (wel) bit, wrenv is used only t o direct the following wrr command to change the volat ile status and configuratio n register bit values. cs# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on si/io0. withou t cs# being driven to the logic high state after the eighth bit of the instruction byte has been latch ed in on si/io0, the write enab le operation will not be executed. figure 45. write enable for volatile registers (wrenv) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 46. write enable for volatile re gisters (wrenv) command sequence qpi mode cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction document number: 002-00124 rev. *f page 75 of 158 s25fl256l/S25FL128L 8.3.8 clear status register (clsr 30h) the clear status register command clears the wip (sr1v[0]), wel (sr1 v[1]), p_err (sr2v[5]), an d e_err (sr2v[6]) bits to ?0?. it is not necessary to set the wel bit before a clear status register command is executed. the clear status register comma nd will be accepted even when the device remains busy with wip set to 1, as the device does remain busy when either error bit is s et. figure 47. clear status register (clsr) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 48. clear status register (clsr) qpi mode 8.3.9 program dlrnv (pdlrnv 43h) before the program dlrnv (pdlrnv) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) to enable the pdlrnv operation. the pdlrnv command is entered by shifting t he instruction and the data byte on si/io0. cs# must be driven to the logic high state after the eighth (8th) bit of data has bee n latched. if not, the pdlrnv command is n ot executed. as soon as cs# is driven to t he logic high state, the self-timed pdlrnv operation is initiated. while the pdlrnv operation is in progress, the status regi ster may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a ?1? during the self-timed pdlrnv cycle, a nd a is 0 when it is completed. the pdlrnv operation can repor t a program error in the p_err bit of the st atus register. when the pdlrnv operation is completed, the write enable latch (wel) i s set to a ?0?. the maximum clock frequency for the pdlrnv command is 133 mhz. figure 49. program dlrnv (pdlrnv) command sequence this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data document number: 002-00124 rev. *f page 76 of 158 s25fl256l/S25FL128L figure 50. program dlrnv (pdlrnv) command sequence ? qpi mode 8.3.10 write dlrv (wdlrv 4ah) before the write dlrv (wdlrv) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) comman d has been decoded successfully, the device will set the write enable latch (wel) to enable wdlrv operation. the wdlrv command is entered by shifting the instruction and the data byte on si/io0. cs# must be driven to the logic high state after the eighth (8th) bit of data has bee n latched. if not, the wdlrv command is no t executed. as soon as cs# is driven to the logic high state, the wdlrv operation is initiated with no delays. the maximum clock frequency for the wdlrv command is 133 mhz. figure 51. write dlrv (wdlrv) command sequence this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3. figure 52. write dlrv (wdlrv) command sequence ? qpi mode cs# sclk io0 io1 io2 io3 phase 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 instruct. input data cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sclk io0 io1 io2 io3 phase 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 instruct. input data document number: 002-00124 rev. *f page 77 of 158 s25fl256l/S25FL128L 8.3.11 data learning pa ttern read (dlprd 41h) the instruction 41h is shif ted into si/io0 by the rising ed ge of the sck signal followed by one dummy cycle. this latency perio d allows the device?s internal circuitry enough time to access da ta at the initial address. during latency cycles, the data value on io0- io3 are ?don?t care? and may be high impedance. then the 8-bit dlp is shifted out on so/io1. it is possible to read the dlp continuously by providing multiples of eight clock cycles. th e maximum operating clock frequency for the dlprd command is 133mhz. figure 53. dlp read (dlprd) command sequence this command is also supported in qpi mode. in qpi mode th e instruction is shifted in and returning data out on io0-io3. figure 54. dlp read (dlprd) command sequence ? qpi mode 8.3.12 enter 4 byte addr ess mode (4ben b7h) the enter 4 byte address mode (4ben) command sets the volatile address length status (ads) bit (cr2v[0]) to 1 to change all 3 byte address commands to require 4 bytes of address. this command will not affect 4 byte only commands which will still continue to expect 4 bytes of address. to return to 3 byte address mode the 4bex command clears th e volatile address length bit cr2v[0]=0). the wrar command can also clear the volatile address length bit cr2v[0]=0). also, a har dware or software reset may be used to return to the 3 byte address mode if the non-volatile address length bit cr2nv[1] = 0. figure 55. enter 4 byte address mode (4ben b7h) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction dy register read repeat register read cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 instruct. dummy register read register read cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction document number: 002-00124 rev. *f page 78 of 158 s25fl256l/S25FL128L figure 56. enter 4 byte address qpi mode 8.3.13 exit 4 byte address mode (4bex e9h) the exit 4 byte address mode (4bex) command sets the volatile address length status (ads) bit (cr2v[0]) to 0 to change most 4 byte address commands to require 3 bytes of address. this command will not affect 4 byte only commands which will still continue to expect 4 bytes of address. figure 57. exit 4 byte address mode (4bex e9h) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 58. exit 4 byte address qpi mode 8.3.14 read any re gister (rdar 65h) the read any register (rdar) command provides a way to read de vice registers. the instruction is followed by a 3 or 4 byte address (depending on the address length config uration cr2v[0]), followed by a num ber of latency (dummy) cycles set by cr3v[3:0]. then the selected register cont ents are returned. if the read access is continued the same add ressed register conten ts are returned until the command is terminated - on ly one register is read by each rdar command. reading undefined locations provides undefined data. the rdar command may be used during embedded operations to read status register 1 (sr1v). the rdar command is not used for reading registers that act as a window into a larger array: iblar. there are separate commands required to select and read the location in the array accessed. the rdar command will read invalid data from the pass register locations if the irp password pr otection mode is selected by programming irp[2] to 0. cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction document number: 002-00124 rev. *f page 79 of 158 s25fl256l/S25FL128L table 41. register address map byte address (hex) register name description 000000 sr1nv non-volatile status and configuration registers reading of non-volatile status and configuration registers actually reads the volatile registers 000001 n/a 000002 cr1nv 000003 cr2nv 000004 cr3nv 000005 nvdlp ... n/a 000020 pass[7:0] non-volatile password register 000021 pass[15:8] 000022 pass[23:16] 000023 pass[31:24] 000024 pass[39:32] 000025 pass[47:40] 000026 pass[55:48] 000027 pass[63:56] ... n/a 000030 irp[7:0] non-volatile 000031 irp[15:8] ... n/a 000039 prpr[a15:a8] pointer region protection register a15:a8 00003a prpr[a23:a16] pointer region protection register a23:a16 00003b prpr[a31:a24] pointer region protection register a31:a24 ... n/a 800000 sr1v volatile status and configuration registers 800001 sr2v 800002 cr1v 800003 cr2v 800004 cr3v 800005 vdlp ... n/a 800040 pr volatile protection register ... n/a document number: 002-00124 rev. *f page 80 of 158 s25fl256l/S25FL128L figure 59. read any register read command sequence note: 1. a = msb of address = 23 for address length cr2v[0] = 0, or 31 for cr2v[0]=1. this command is also supported in qpi mode. in qpi mode the in struction and address is shifted in and returning data out on io0 - io3. figure 60. read any register, qpi mode, command sequence note: 1. a = msb of address = 23 for address length cr2v[0] = 0, or 31 for cr2v[0]=1 8.3.15 write any register (wrar 71h) the write any register (wrar) command prov ides a way to write any device register - non-volatile or volatile. the instruction i s followed by a 3 or 4 byte address (depending on the address length configuration cr2v[0]), followed by one byte of data to write in the address selected register. the s25fl256l device must have 4 byte addressing enabled (cr2v[0] = 1) to set the pointer region protection register prpr (see section 6.6.10 on page 43 ). before the wrar command can be accepted by the device, a wr ite enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wip bit in sr1v may be checked to determine when the operation is completed. the p_e rr and e_err bits in sr2v may be checked to determine if any error occurred during the operation. some registers have a mixture of bit types and individual rules controlling which bits may be modified. some bits are read only , some are otp. read only bits are never modified and the related bits in the wr ar command data byte are ignored without setting a program or erase error indication (p_err or e_err in sr2v). hence, the value of these bits in the wrar data byte do not matter. otp bits may only be programmed to the level opposite of their de fault state. writing of otp bits back to their default state i s ignored and no error is set. non-volatile bits which are changed by the wrar data, require non-volatile register write time (t w ) to be updated. the update process involves an erase and a program operation on the non-volat ile register bits. if either th e erase or program portion of the update fails the related error bit in sr2v and wip in sr1v will be set to 1. volatile bits which are changed by the wrar data, require the volatile register write time (t cs ) to be updated. status register 1 may be repeatedly read (polled) to monitor th e write-in-progress (wip) bit (s r1v[0]) to determine when the register write is completed and status regi ster 2 for the error bits (sr2v[6,5]) to determine if there is write failure. if the re is a write failure, the clear status command is used to clear the error status and enable the dev ice to return to standby state. when the wrar operation is completed, the write en able latch (wel) is set to a ?0? . cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address dummy data data data data document number: 002-00124 rev. *f page 81 of 158 s25fl256l/S25FL128L however, the pr register can not be written by the wrar command . the pr register contents are treated as read only bits. only the nvlock bit write (prl) command can write the pr register. the wrar command to write the sr1nv, cr1nv cr2nv and cr3nv is protected from a hardware and software reset, the wrar command to all other register are reset from a hardware or software reset. the wrar command sequence and behavior is the same as the pp or 4pp command with only a single byte of data provided. see section 8.5.2, page program (pp 02h or 4pp 12h) on page 92 . the address map of the registers is the same as shown for table 41, register address map on page 79 . 8.3.16 set burst length (sbl 77h) the set burst length (sbl) command is used to configure the burst wrap fe ature. burst wrap is used in conjunction with quad i/o read and ddr quad i/o read, in qio or qpi modes, to access a fixed length and alignment of data. certain applications can benefit from this feature by improving t he overall system code execution performance. the burst wrap featur e allows application s that use cache, to start filling a cache li ne with instruction or data from a critic al address first, then fill the remainder o f the cache line afterwards within a fixed length (8/16/32/64-byte s) of data, without issuing multiple read commands. the set burst length command is initiated by driving the cs# pin low and then shifting the instruction code ?77h? followed by 2 4 dummy bits and 8 ?wrap length bits (wl[7]-w l[0])?. the command sequence is shown in figure 61, set burst length command sequence quad i/o mode on page 82 and figure 62, set burst length command sequence qpi mode on page 83 . wrap length bit wl[7] and the lower nibble wl[3:0] are not used. see configur ation register 3 (cr3v[6:4]) fo r the encoding of wl[6]-wl[4] i n section 6.6.5, configuration register 3 on page 36 . once wl[6:4] is set by a set burst length command, all the foll owing ?quad i/o read? commands will use the wl[6:4] setting to access the 8/16/32/64-byte secti on of data. note, configuration register 1 quad bit cr1v[1] or configuration register 2 qpi bit cr2v[3] must be set to 1 in order to use the quad i/o read and set burst length commands. to exit the ?wrap around? function an d return to normal read operation, another set burst with wrap co mmand should be issued to set wl4 = 1. the default value of wl[6:4] upon power on, hardware or software reset as set in the cr2nv[6:5]. use wrr or wrar command to set the default wrap length in cr2nv[6;2]. the set burst length (sbl) command writes only to cr3v[6:4] bits to enable or disable the wra pped read feature and set the wrap boundary. the sbl command cannot be used to set the read late ncy in cr3v[3:0]. the wrar command must be used to set the read latency in cr3v or cr3nv. see table 42, example burst wrap sequences on page 82 for cr3v[6:5] values for wrap boundary's and start address. when enabled the wrapped read feature changes the related read commands from sequentially reading until the command ends, to reading sequentially wrapped within a group of bytes. when the wrap mode is not enabled ( table 6.15 and table 21 ), an unlimited length sequential read is performed. when the wrap mode is enabled ( table 6.15 and table 21 ) a fixed length and aligned group of 8, 16, 32, or 64 bytes is read starting at the byte address provided by the read command a nd wrapping around at the group alignment boundary. the group of bytes is of length and aligned on an 8, 16, 32, or 64 byte boundary. cr3v[6:5] selects the boundary. see section 6.6.5.2, configuration register 3 volatile (cr3v) on page 40 . the starting address of the read command sele cts the group of bytes and the first data returned is the addressed byte. bytes ar e then read sequentially until the end of the group boundary is reached. if the read cont inues the address wraps to the beginning of the group and continues to read sequentially. this wrapped read sequence continues until the command is ended by cs# returning high. document number: 002-00124 rev. *f page 82 of 158 s25fl256l/S25FL128L the power-on reset, hardware reset, or software reset default bu rst length can be changed by programming cr3nv with the desired value using the wrar command. figure 61. set burst length command sequence quad i/o mode table 42. example burst wrap sequences cr3v value (hex) wrap boundary (bytes) start address (hex) address sequence (hex) 1x sequential xxxxxx03 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c , 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, ... 00 8 xxxxxx00 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ... 00 8 xxxxxx07 07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ... 01 16 xxxxxx02 02, 03, 04, 05, 06, 07, 08, 09, 0a , 0b, 0c, 0d, 0e, 0f, 00, 01, 02, 03, ... 01 16 xxxxxx0c 0c, 0d, 0e, 0f, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, ... 02 32 xxxxxx0a 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, ... 02 32 xxxxxx1e 1e, 1f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 00, ... 03 64 xxxxxx03 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c , 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3a, 3b, 3c, 3d, 3e, 3f, 00, 01, 02, ... 03 64 xxxxxx2e 2e, 2f, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3a, 3b, 3c, 3d, 3e, 3f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d,, ... cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 x x x x x x wl4 x x x x x x x wl5 x x x x x x x wl6 x x x x x x x x x instruction don't care wrap document number: 002-00124 rev. *f page 83 of 158 s25fl256l/S25FL128L figure 62. set burst length command sequence qpi mode 8.3.17 enter qpi mode (qpien 38h) the enter qpi mode (qpien) command enables the qpi mode by setting the volatile qpi bit (cr2v[3]=1). see table 16, configuration register 2 volatile (cr2v) on page 35 . the time required to enter qpi mode is t qen , see table 60, sdr ac characteristics on page 139 , no other commands are allowed during the t qen transition time to qpi mode. to return to spi mode the qpiex command or a write to register (cr2v[3]=0) is required. a power on reset, hardware, or software reset will also return the part to spi mode if the non-volatile qpi (cr2nv[3]=0). see table 14, configuration register 2 non-volatile (cr2nv) on page 34 . figure 63. enter qpi mode (qpien 38h) command sequence 8.3.18 exit qpi mode (qpiex f5h) the exit qpi mode (qpiex) command disables the qpi mode by setti ng the volatile qpi bit (cr2v[ 3]=0) and returning to spi mode. see table 16, configuration regist er 2 volatile (cr2v) on page 35 . the time required to exit qpi mode is t qex , see table 60, sdr ac characteristics on page 139 , no other commands are allowed during the t qex transition time to exit the qpi mode. figure 64. exit qpi (qpiex f5h) command sequence cs# sclk io0 io1 io2 io3 phase 4 0 x x x x x x wl4 x 5 1 x x x x x x wl5 x 6 2 x x x x x x wl6 x 7 3 x x x x x x x x instruct. don't care wrap cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction document number: 002-00124 rev. *f page 84 of 158 s25fl256l/S25FL128L 8.4 read memory array commands read commands for the main flash array provide many options fo r prior generation spi compatibilit y or enhanced performance spi: ? some commands transfer address or data on each rising e dge of sck. these are called single data rate commands (sdr). ? some sdr commands transfer address one bit per falling edge of sck and return data 1bit of data per rising edge of sck. these are called single width commands. ? some sdr commands transfer both address and data 2 or 4 bits per rising edge of sck. these are called dual i/o for 2 bit, quad i/o, and qpi for 4 bit. qpi also transfers instructions 4 bits per rising edge. ? some commands transfer address and data on both the rising edge and falling edge of sck. these are called double data rate (ddr) commands. ? there are ddr commands for 4 bits of address or data pe r sck edge. these are called quad i/o ddr and qpi ddr for 4 bit per edge transfer. all of these commands, except qpi read, beg in with an instruction code that is transf erred one bit per sck rising edge. qpi rea d transfers the instruction 4 bits per sck rising edge.the instruct ion is followed by either a 3 or 4 byte address transferred at sdr or ddr. commands transferring address or data 2 or 4 bits per clock edge are called multiple i/o (mio) commands. for fl-l family devices at 256mb or higher density, the tr aditional spi 3 byte addresses are unable to directly address all locations in the me mory array. separate 4 byte address read comm ands are provided for access to the entire address space. these devices may be configured to take a 4 byte address from the host system with the traditional 3 byte address commands. the 4 byte address mode for traditional commands is activated by setting the address leng th bit in configuration register 2 to ?1?. in the S25FL128L hi gher order address bits above a23 in the 4 byte address commands, or commands using 4 byte address mode are not relevant and are ignored because the flash array is only 128mb in size. the dual i/o, quad i/o and qpi commands provide a performance improvement option controlled by mode bits that are sent following the address bits. the mode bits indicate whether the command following the end of the current read will be another re ad of the same type, without an instruction at the beginning of the read. these mode bits give the option to eliminate the instructio n cycles when doing a series of dual or quad read accesses. some commands require delay cycles following the address or mode bits to allow time to acce ss the memory array - read latency. the delay or read latency cycles are traditionally called dummy cycl es. the dummy cycles are ignored by the memory thus any dat a provided by the host during these cycles is ?don?t care? and the host may also leave the si signal at high impedance during the dummy cycles. when mio commands are used th e host must stop driving the io signals (outputs are high impedance) before the end of last dummy cycle. when ddr commands are used the host must not drive the i/o signals during any dummy cycle. the number of dummy cycles varies with the sck frequency or per formance option selected via th e configuration register 2 (cr3v[3:0]) latency code. dummy cycles are measured from sc k falling edge to next sck falling edge. spi outputs are traditionally driven to a new value on the falling edge of each sck. zero dummy cycles means the returning data is driven by th e memory on the same falling edge of sck that t he host stops driving address or mode bits. the ddr commands may optionally have an 8 edge data learning patte rn (dlp) driven by the memory, on all data outputs, in the dummy cycles immediately before the start of data. the dlp can help the ho st memory controller dete rmine the phase shift from sck to data edges so that the memory controller can capture data at the center of the data eye. when using sdr i/o commands at higher sck frequencies (>50 mh z), an lc that provides 1 or more dummy cycles should be selected to allow additional time for the host to stop driving bef ore the memory starts driving data, to minimize i/o driver co nflict. when using ddr i/o commands with the dlp enab led, an lc that provides 5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle dlp. each read command ends when cs# is returned high at any point during data return. cs# must not be returned high during the mode or dummy cycles before data returns as this may cause mode bi ts to be captured in correctly; making it indeterminate as to whether the device remains in continuous read mode. document number: 002-00124 rev. *f page 85 of 158 s25fl256l/S25FL128L 8.4.1 read (read 03h or 4read 13h) the instruction ? 03h (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? 03h (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? 13h is followed by a 4-byte address (a31-a0) then the memory contents, at the addre ss given, are shifted out on so/io1. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 65. read command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command 13h. 8.4.2 fast read (fast_read 0bh or 4fast_read 0ch) the instruction ? 0bh (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? 0bh (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? 0ch is followed by a 4-byte address (a31-a0) the address is followed by dummy cycles depending on the latency code set in the configuration register cr3v[3:0]. the dummy cycles allow the device internal circuits additional time for accessing the initial address locati on. during the dummy cycles t he data value on so/io1 is ?don?t care? and may be high impedance. t hen the memory contents, at the address given, are shifted out on so/io1. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 66. fast read (fast_read) command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command 0ch. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data n cs# sck si_io0 so_io1 io2-io3 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 document number: 002-00124 rev. *f page 86 of 158 s25fl256l/S25FL128L 8.4.3 dual output read (dor 3bh or 4dor 3ch) the instruction ? 3bh (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? 3bh (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? 3ch is followed by a 4-byte address (a31-a0) the address is followed by dummy cycles depending on the latency code set in the configuration register cr3v[3:0]. the dummy cycles allow the device internal circuits additional time for accessing the initial address locati on. during the dummy cycles t he data value on io0 (si) and io1 (s0) is ?d on?t care? and may be high impedance. then the memory contents, at the address given, is shifted out tw o bits at a time through io0 (si) and io1 (so). two bits are s hifted out at the sck frequency by the falling edge of the sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. for dual output read commands, there are dummy cycles required af ter the last address bi t is shifted into io0 (si) before data begins shifting out of io0 and io1. figure 67. dual output read command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command 3ch. 8.4.4 quad output read (qor 6bh or 4qor 6ch) the instruction ? 6bh (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? 6bh (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? 6ch is followed by a 4-byte address (a31-a0) the address is followed by dummy cycles depending on the latency code set in the configuration register cr3v[3:0]. the dummy cycles allow the device internal circuits additional time for accessing the initial address locati on. during the dummy cycles t he data value on io0 - io3 is ?don?t care? and may be high impedance. then the memory contents, at the address give n, is shifted out four bits at a time th rough io0 - io3. each nibble (4 bits) is s hifted out at the sck frequency by the falling edge of the sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. for quad output read commands, there are dummy cycles required after t he last address bit is shi fted into io0 before data begin s shifting out of io0 - io3. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 a 1 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address dummy cycles data 1 data 2 document number: 002-00124 rev. *f page 87 of 158 s25fl256l/S25FL128L figure 68. quad output read command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command 6ch. 8.4.5 dual i/o read (d ior bbh or 4dior bch) the instruction ? bbh (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? bbh (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? bch is followed by a 4-byte address (a31-a0) the dual i/o read commands improve throughput with two i/o signal s ? io0 (si) and io1 (so). this command takes input of the address and returns read data two bits per sck rising edge. in some applications, the reduced address input and data output tim e might allow for code execution in place (xip) i.e. directly from the memory device. the dual i/o read command has continuous read mode bits that follow the address so, a series of dual i/o read commands may eliminate the 8 bit instruction after the first dual i/o read co mmand sends a mode bit pattern of axh that indicates the follow ing command will also be a dual i/o read command. the first dual i/ o read command in a series starts with the 8 bit instruction, followed by address, followed by four cycles of mode bits, fo llowed by an optional latency period. if the mode bit pattern is a xh the next command is assumed to be an additional dual i/o read comma nd that does not provide instruct ion bits. that command starts with address, followed by mode bits, followed by optional latency. variable latency may be added after the mode bits are shifted into si and so before data begins shifting out of io0 and io1. th is latency period (dummy cycles) allows the de vice internal circuitry enough time to a ccess data at the initia l address. during th e dummy cycles, the data value on si and so are ?don?t care? and may be high imp edance. the number of dummy cycles is determined by the frequency of sck. the latency is configured in cr3v[3:0]. the continuous read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code execution (xip) performance. the upper nibble (bits 7-4) of the mode bits control the le ngth of the next dual i/o read command through the inclusion or exclusion of the fi rst byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?) and may be high impedance. if the mode bits equal axh, then the device remains in dual i/o continuous read mode and the next address can be entered (after cs# is raised high and then asse rted low) without the bbh or bc h instruction, as shown in figure 70 ; thus, eliminating eight cycles of the comm and sequence. the following sequences will re lease the device from dual i/o continuou s read mode; after which, the device can accept standard spi commands: 1. during the dual i/o continuous read command sequence, if t he mode bits are any value ot her than axh, then the next time cs# is raised high the device will be re leased from dual i/o conti nous read mode. 2. send the mode reset command. note that the four mode bit cycles are part of the device?s in ternal circuitry latency time to access the initial address after the last address cycle that is clocke d into io0 (si) and io1 (so). it is important that the i/o signals be set to high-impedance at or before the falling edge of t he first data out clock. at hig her clock speeds the time available to turn off the host outputs before th e memory device begins to drive (b us turn around) is diminished . it is allowed and may be helpful in preventing i/o signal contention, for the host system to turn of f the i/o signal outputs (make th em high impedance) during the last two ?don?t care? mode cycles or during any dummy cycles. following the latency period the memory conten t, at the address given, is shifted out two bits at a time through io0 (si) and i o1 (so). two bits are shifted out at the sck frequency at the falling edge of sck signal. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address dummy d1 d2 d3 d4 d5 document number: 002-00124 rev. *f page 88 of 158 s25fl256l/S25FL128L the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. figure 69. dual i/o read command sequence notes: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command bch. 2. least significant 4 bits of mode are don?t care and it is opt ional for the host to drive these bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 70. dual i/o continuous read command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command bch. 8.4.6 quad i/o read (q ior ebh or 4qior ech) the instruction, ? ebh (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? ebh (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? ech is followed by a 4-byte address (a31-a0) the quad i/o read command improves throughput with four i/o signals io0-io3. it allows input of the address bits four bits per serial sck clock. in some applications, the reduced instruction overhead might allow for code exec ution (xip) directly from fl- l family devices. the quad bit of the configuration register 1 mu st be set (cr1v[1]=1) or the qpi bit of configuration register 2 must be set (cr2v[1]=1 to enable the quad capability of fl-l family devices. for the quad i/o read command, there is a latency required after the m ode bits (described below) before data begins shifting ou t of io0-io3. this latency period (i.e., dummy cycles) allows the de vice?s internal circuitry enough time to access data at the init ial address. during latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck. the latency is configured in cr3v[3:0]. following the latency period, the memory co ntents at the address given, is shifted out four bits at a time through io0-io3. eac h nibble (4 bits) is shifted out at the sck fr equency by the falling edge of the sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 a-1 2 0 6 4 2 0 6 4 2 0 6 4 2 0 a 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sck io0 io1 phase 6 4 2 0 a-1 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 a 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dum data 1 data 2 document number: 002-00124 rev. *f page 89 of 158 s25fl256l/S25FL128L address jumps can be done without the need for additional quad i/o read instructions. this is controlled through the setting of the mode bits (after the address sequence, as shown in figure 71 on page 89 . this added feature removes the need for the instruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of t he mode bits control the length of the next quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?). if the mode bits equal axh, then the dev ice remains in quad i/o high performance read mode and the next address can be entered (after cs# is raised high and then assert ed low) without requiring the ebh or ech instruction, as shown in figure 73 on page 90 ; thus, eliminating eight cycles for the command seq uence. the following sequences will release the device from quad i/o high performance read mode; after which, the device can acce pt standard spi commands: 1. during the quad i/o read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from quad i/o high performance read mode. 2. send the mode reset command. note that the two mode bit clock cycles an d additional wait states (i.e., dummy cycles) allow the device?s internal circuitry l atency time to access the initial addr ess after the last address cycle that is clocked into io0-io3. it is important that the io0-io3 signals be set to high-impedanc e at or before the falling edge of the first data out clock. at higher clock speeds the time available to turn off the host outputs befo re the memory device begins to drive (bus turn around) is dimi nished. it is allowed and may be helpful in preventing io0-io3 signal cont ention, for the host system to turn off the io0-io3 signal ou tputs (make them high impedance) during the last ?don ?t care? mode cycle or during any dummy cycles. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. in qpi mode (cr2v[3]=1) the quad i/o instru ctions are sent 4 bits per sck rising edge. the remainder of the command protocol is identical to the quad i/o commands. figure 71. quad i/o read initial access command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command ech. figure 72. quad i/o read initial access command sequence qpi mode note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command ech. cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a-3 4 0 4 0 4 0 4 0 4 0 4 0 a-2 5 1 5 1 5 1 5 1 5 1 5 1 a-1 6 2 6 2 6 2 6 2 6 2 6 2 a 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4 document number: 002-00124 rev. *f page 90 of 158 s25fl256l/S25FL128L figure 73. continuous quad i/o read command sequence note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command ech. 2. the same sequence is used in qpi mode. 8.4.7 ddr quad i/o read (edh, eeh) the ddr quad i/o read command improves throughput with four i/o si gnals io0-io3. it is similar to the quad i/o read command but allows input of the address four bits on every edge of the clock. in some applic ations, the reduced instruction overhead mi ght allow for code execution (xip) directly from fl-l family device s. the quad bit of the config uration register 1 must be set (cr1v[1]=1) or the qpi bit of configuration register 2 must be set (cr2v[1]=1 to enabl e the quad capability of fl-l family devi ces. the instruction ? edh (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? edh (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? eeh is followed by a 4-byte address (a31-a0) the address is followed by mode bits. then the memory contents, at the address given, is shifted out, in a ddr fashion, with fo ur bits at a time on each clock edge through io0-io3. the maximum operating clock frequency for ddr quad i/o read command is 66 mhz. for ddr quad i/o read, there is a latency required after the last address and mode bits are shifted into the io0-io3 signals be fore data begins shifting out of io0-io3. this latency period (dummy cycles) allows the device?s in ternal circuitry enough time to a ccess the initial address. during these latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. when th e data learning pattern (dlp) is enabled the host system must not drive the io signals during the dummy cycles. the io signals mu st be left high impedance by the host so that the memory device can dr ive the dlp during the dummy cycles. the number of dummy cycles is determined by the fre quency of sck. the latency is configured in cr3v[3:0]. mode bits allow a series of quad i/o ddr commands to elim inate the 8 bit instruction after the first command sends a complementary mode bit pattern. this feature removes the need fo r the eight bit sdr instruction sequence and dramatically reduc es initial access times (improves xip performance). the mode bits c ontrol the length of the next ddr quad i/o read operation throu gh the inclusion or exclusion of the first by te instruction code. if the upper nibble (io[7 :4]) and lower nibble (io[3:0]) of the mode bits are complementary (i.e. 5h and ah) the device transitions to co ntinuous ddr quad i/o read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the edh or eeh instruction, thus eliminating eight c ycles from the command sequence. the following sequences will rel ease the device from continuous ddr quad i/o read mode; after which, the device can accept standard spi commands: 1. during the ddr quad i/o read command sequence, if the mode bits are not complementary the next time cs# is raised high and then asserted low the device will be released from ddr quad i/o read mode. 2. send the mode reset command. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# sck io0 io1 io2 io3 phase 4 0 4 0 a-3 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 a-2 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 a-1 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 a 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4 document number: 002-00124 rev. *f page 91 of 158 s25fl256l/S25FL128L cs# should not be driven high during mode or dummy bits as this may make the mode bits indete rminate. note that the memory devices may drive the ios with a preamble prior to the first data value. the preamble is a data learning pattern (dlp) that is used by the host controller to optimize data capture at higher frequencies. the preamble drives the io bus for the four clock cycles immediately before data is output. the host must be sure to stop driving the io bus prior to th e time that the memory starts outputting the preamble. the preamble is intended to give the host controller an indicati on about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. the host controller will skew the data capture point during t he preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. the optimized capture point wil l be determined during the preamble period of every read operation. this optimization strategy is intended to compensate for both the pvt (process, vo ltage, temperature) of both t he memory device and the host controller as well as any system level delays caused by flight time on the pcb. although the data learning pattern (dlp) is programmable, t he following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on each of the active outputs (i.e. all four ios). this pattern was chosen to cover both ?dc? and ?ac? data transition scenarios. the two dc transition scenarios include data low for a long period of time (two half clocks) followe d by a high going transition (001) and the complementary low going tran sition (110). the two ac transition scenarios include data low for a short period of time (one half clock) followed by a high going transition (101) and the comple mentary low going transition (010 ). the dc transitions will typically occur with a starting point closer to the supply rail than the ac transitions that may not have f ully settled to their steady state (dc) levels. in many cases the dc trans itions will bound the beginning of the data valid period and the a c transitions will bound the ending of the data valid period. thes e transitions will allow the host controller to identify the be ginning and ending of the valid data eye. once the dat a eye has been characterized the optimal dat a capture point can be chosen. in qpi mod e (cr2v[3]=1) the ddr quad i/o instructions are sent 4 bits at sck rising edge. the remainder of t he command protocol is identica l to the ddr quad i/o commands. figure 74. ddr quad i/o read initial access notes: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command eeh 2. example dlp of 34h (or 00110100) figure 75. ddr quad i/o read initial access qpi mode note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command eeh. 2. example dlp of 34h (or 00110100). cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 a 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2 cs# sclk io0 io1 io2 io3 phase 4 0 a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 5 1 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 6 2 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 7 3 a 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruct. address mode dummy dlp d1 d2 document number: 002-00124 rev. *f page 92 of 158 s25fl256l/S25FL128L figure 76. continuous ddr quad i/o read subsequent access note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1 or command eeh. 2. the same sequence is used in qpi mode. 3. example dlp of 34h (or 00110100). 8.5 program flash array commands 8.5.1 program granularity 8.5.1.1 page programming page programming is done by loading a page buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. this sets an upper limit on the amount of data that can be programmed with a single programming command. page programming allows up to a page size 256bytes to be programmed in one operation. the page is aligned on the page size address boundary. it is possible to program from one bit up to a page size in each page programming operation. for the very best performance, programming should be done in full pages of 256bytes aligned on 256byte boundaries with each page being programmed only once. 8.5.1.2 single byte programming single byte programming allows full back ward compatibility to the legacy standard spi page programming (pp) command by allowing a single byte to be programmed anywhere in the memory array. 8.5.2 page program (pp 02h or 4pp 12h) the page program (pp) command allows bytes to be programmed in the memory (changing bits from 1 to 0). before the page program (pp) commands can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device sets the write enable latch (wel) in the status register to e nable any write operations. the instruction ? 02h (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? 02h (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? 12h is followed by a 4-byte address (a31-a0) and at least one data byte on si/io0. up to a page can be prov ided on si/io0 after the 3-byte address with instruction 02h or 4 -byte address with instruction 12h has been provided . as with the write and erase commands, t he cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program command will no t be executed. after cs# is d riven high, the self-timed page program command will commence for a time duration of t pp . using the page program (pp) command to load an entire page , within the page boundary, will save overall programming time versus loading less than a page into the program buffer. the programming process is managed by the flash memory device in ternal control logic. after a programming command is issued, the programming operation status can be checked using the read status register 1 command. the wip bit (sr1v[0]) will indicate when the programming operation is completed. the p_err bit (sr2 v[5]) will indicate if an error occurs in the programming operation that prevents successful completion of programming. this includes attempted progr amming of a protected area. cs# sck io0 io1 io2 io3 phase a-3 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 1 a-2 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 2 a-1 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 a 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 address mode dummy dlp d1 d2 document number: 002-00124 rev. *f page 93 of 158 s25fl256l/S25FL128L figure 77. page program (pp 02h or 4pp 12h) command sequence note: 1. a = msb of address = a23 for pp 02h with cr2v[0]=0, or a31 for pp 02h with cr2v[0]=1, or for 4pp 12h. this command is also supported in qpi mode. in qpi mode the instruction, address and data is shifted in on io0-io3. figure 78. page program (pp 02h or 4pp 12h) qpi mode command sequence note: 1. a = msb of address = a23 for pp 02h with cr2v[0]=0, or a31 for pp 02h with cr2v[0]=1, or for 4pp 12h. 8.5.3 quad page program (qpp 32h or 4qpp 34h) the quad-input page program (qpp) command allo ws bytes to be programmed in the memory (changing bits from 1 to 0). the quad-input page program (qpp) command allows up to a page of da ta to be loaded into the page buffer using four signals: io0- io3. qpp can improve performance for prom programmer and applicat ions that have slower clock speeds (< 12 mhz) by loading 4 bits of data per clock cycle. systems with faster clock speeds do not realize as much benefit for the qpp command since the inherent page program time becomes greater than the time it takes to clock-in the data. the maximum frequency for the qpp command is 133mhz. to use quad page program the quad enable bit in the config uration register must be set (q uad=1). a write enable command must be executed before the device will accept the qpp command (status register 1, wel=1). the instruction ? 32h (cr2v[0]=0) is followed by a 3-byte address (a23-a0) or ? 32h (cr2v[0]=1) is followed by a 4-byte address (a31-a0) or ? 34h is followed by a 4-byte address (a31-a0) and at least one data byte, into the io signals. data must be programmed at previously erased (ffh) memory locations. all other functions of qpp are identical to page program. the qpp command sequence is shown in the figure below. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2 cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address input d1 input d2 input d3 input d4 document number: 002-00124 rev. *f page 94 of 158 s25fl256l/S25FL128L figure 79. quad page program command sequence note: 1. a = msb of address = a23 for qpp 32h with cr2v[0]=0, or a31 for qpp 32h with cr2v[0]=1, or for 4qpp 34h. 8.6 erase flash array commands 8.6.1 sector erase ( se 20h or 4se 21h) the sector erase (se) command sets all bits in the addressed se ctor to 1 (all bytes are ffh). before the sector erase (se) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? 20h [cr2v[0]=0] is followed by a 3-byte address (a23-a0), or ? 20h [cr2v[0]=1] is followed by a 4-byte address (a31-a0), or ? 21h is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high state after the twenty-four th or thirty-second bit of the address has been latched in on si/io0. this will initiate the beginning of internal erase cycle, which in volves the pre-programming and erase of the chosen sector of the flash memory array. if cs# is not driven high after the last bit of address, the sector er ase operation will not be executed. as soon as cs# is driven high, the internal erase cycle will be initiated. with the internal erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a ?1 ?. when the erase cycle is in progress and a ?0? when the erase cycle has been completed. a se or 4se command applied to a sector that has been write protected through the legacy block protection, individual block loc k or pointer region protection will not be executed and will set the e_err status. figure 80. sector erase (se 20h or 4se 21h) command sequence note: 1. a = msb of address = a23 for se 20h with cr2v[0]=0, or a31 for se 20h with cr2v[0]=1 or for 4se 21h. this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0-io3. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address data 1 data 2 data 3 data 4 data 5 ... cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 instruction address document number: 002-00124 rev. *f page 95 of 158 s25fl256l/S25FL128L figure 81. sector erase (se 20h or 4se 21h) qpi mode command sequence note: 1. a = msb of address = a23 for se 20h with cr2v[0]=0, or a31 for se 20h with cr2v[0]=1 or for 4se 21h. 8.6.2 half block erase (h be 52h or 4hbe 53h) the half block erase (hbe) command sets all bits in the address ed half block to 1 (all bytes are ffh). before the half block er ase (hbe) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enab le any write operations. the instruction ? 52h [cr2v[0]=0] is followed by a 3-byte address (a23-a0), or ? 52h [cr2v[0]=1] is followed by a 4-byte address (a31-a0), or ? 53h is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high st ate after the twenty-fourth or thirty-second bit of addres s has been latched in on si/ io0. this will initiate the erase cycle, which involves the pre-programming and erase of each sector of the chose block. if cs# is not dr iven high after the last bit of address, the half block erase operatio n will not be executed. as soon as cs# is driven into the logic high state, the internal erase cycle will be in itiated. with the internal erase cycle i n progress, the user can read the value of the write- in progress (wip) bit to check if the operation has been completed. the wip bit will i ndicate a ?1? when the erase cycle is in progress and a ?0? when the erase cycle has been completed. a half block erase (hbe) command applied to a block that has been write protected through the legacy block protection, individual block lock or pointer region protection will not be executed and will set the e_err status. if a half block erase command is applied and if any region, sect or or block in the half block er ase area is prot ected the erase will not be executed on the 32 kb range and will set the e_err status. figure 82. half block erase (hbe 52h or 4hbe 53h) command sequence notes: 1. a = msb of address = a23 for hbe 52h with cr2v[0]=0, or a31 for hbe 52h with cr2v[0]=1 or 4hbe 53h. 2. when a[15]=0 the sectors 0-7 of block are erased and a[15]=1 then sectors 8-15 of block are erased. this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0-io3. cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 instruction address document number: 002-00124 rev. *f page 96 of 158 s25fl256l/S25FL128L figure 83. half block erase (hbe 52h or 4hbe 53h) qpi mode command sequence notes: 1. a = msb of address = a23 for hbe 52h with cr2v[0]=0, or a31 for hbe 52h with cr2v[0]=1 or 4hbe 53h. 2. when a[15]=0 the sectors 0-7 of block are erased and a[15]=1 then sectors 8-15 of block are erased. 8.6.3 block erase (be d8h or 4be dch) the block erase (be) command sets all bits in the addressed block to 1 (all bytes are ffh). before the block erase (be) command can be accepted by the device, a write enable (wren) command must be issued an d decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? d8h [cr2v[0]=0] is followed by a 3-byte address (a23-a0), or ? d8h [cr2v[0]=1] is followed by a 4-byte address (a31-a0), or ? dch is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high st ate after the twenty-fourth or thirty-second bit of addres s has been latched in on si/ io0. this will initiate the erase cycle, which involves the pre-programming and erase of each sector of the chosen block. if cs# is not d riven high after the last bit of address, the block erase operation will not be executed. as soon as cs# is driven into the logic high state, the internal erase cycle will be in itiated. with the internal erase cycle i n progress, the user can read the value of the write- in progress (wip) bit to check if the operation has been completed. the wip bit will i ndicate a ?1? when the erase cycle is in progress and a ?0? when the erase cycle has been completed. a block erase (be) command applied to a block that has been write protected through the lega cy block protection, individual block lock or pointer region protection will not be executed and will set the e_err status. if a block erase command is applied and if any region or sector area is protected the erase wi ll not be executed on the 64 kb ra nge and will set the e_err status. figure 84. block erase (be d8h or 4be dch) command sequence note: 1. a = msb of address = a23 for be d8h with cr2v[0]=0, or a31 for be d8h with cr2v[0]=1 or 4be dch. this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0-io3. cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 instruction address document number: 002-00124 rev. *f page 97 of 158 s25fl256l/S25FL128L figure 85. block erase (be d8h or 4be dch) qpi mode command sequence note: 1. a = msb of address = a23 for be d8h with cr2v[0]=0, or a31 for be d8h with cr2v[0]=1 or 4be dch. 8.6.4 chip erase (ce 60h or c7h) the chip erase (ce) command sets all bits to 1 (all bytes are ff h) inside the entire flash memory array. before the ce command can be accepted by the device, a write enable (wren) command must be issued an d decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. cs# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on si/io0. this w ill initiate the erase cycle, which involves the pre-progr amming and erase of the entire flash memory array. if cs# is not driven high after the last bit of instruction, the ce operation will not be executed. as soon as cs# is driven into the logic high state, the erase cycle will be initiate d. with the erase cycle in progress, the us er can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a ?1? when the erase cycle is in progress an d a ?0? when the erase cycle has been completed. a ce command will not be executed when the legacy block protecti on, individual block lock or pointer region protection set to protect any sector or block and this will set the e_err status bit. figure 86. chip erase command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 87. chip erase command sequence qpi mode cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction document number: 002-00124 rev. *f page 98 of 158 s25fl256l/S25FL128L 8.6.5 program or era se suspend (pes 75h) the pes command allows the system to interrupt a programming or erase operation and then r ead from any other non-erase- suspended sector or non-program-suspended-page . program or erase suspend is valid only during a programming or sector erase, half block erase or block erase operation. a chip erase operation cannot be suspended. the write in progress (wip) bit in status re gister 1 (sr1v[0]) must be checked to kn ow when the programming or erase operation has stopped. the program suspend status bi t in the status register 2 (sr2[0]) ca n be used to determine if a programming operation has been suspended or was complete d at the time wip changes to 0. the eras e suspend status bit in the status register 2 (sr2[1]) can be used to determine if an erase operation has been suspended or was comple ted at the time wip changes to 0. the time required for the suspend operation to complete is t sl , see table 63, program or erase suspend ac parameters on page 144 . an erase can be suspended to allow a program operation or a read operation. during an erase susp end, the ibl array may be read to examine sector protection and written to remove or restore pr otection on a sector to be programmed. the protection bits will not be rechecked when the operation is resumed so any chan ges made will not impact current in progress operation. a program operation may be suspende d to allow a read operation. a new suspend operation is not allowed with-in an already su spended erase or program operation. the suspend command is ignored in this situation. table 43. commands allowed during program or erase suspend instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment read 03 x x all array reads allowed in suspend rdsr1 05 x x needed to read wip to determine end of suspend process rdar 65 x x alternate way to read wip to determine end of suspend process rdsr2 07 x x needed to read suspend status to determine whether the operation is suspended or complete. rdcr1 35 x x needed to read configuration register 1 rdcr2 15 x x needed to read configuration register 2 rdcr3 33 x x needed to read configuration register 3 ruid 4b x x needed to read unique id rdid 9f x x needed to read device id rdqid af x x needed to read quad device id rsfdp 5a x x needed to read sfdp sbl 77 x x needed to set burst length wren 06 x x required for program command within erase suspend wrdi 04 x x required for program command within erase suspend pp 02 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. 4pp 12 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. qpp 32 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. document number: 002-00124 rev. *f page 99 of 158 s25fl256l/S25FL128L note: 1. for all quad commands the quad enable cr1v[1] bit (see table 13 on page 33 ) needs to be set to ?1? before initial program or erase, since the wrr/wrar commands are not allowed inside of the suspend state. 4qpp 34 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. 4read 13 x x all array reads allowed in suspend clsr 30 x x clear status may be used if a program operation fails during erase suspend. epr 7a x x required to resume from erase or program suspend. rsten 66 x x reset allowed anytime rst 99 x x reset allowed anytime fast_read 0b x x all array reads allowed in suspend 4fast_read 0c x x all array reads allowed in suspend dor 3b x x all array reads allowed in suspend 4dor 3c x x all array reads allowed in suspend dior bb x x all array reads allowed in suspend 4dior bc x x all array reads allowed in suspend iblrd 3d x x it may be necessary to remove and restore individual block lock during erase suspend to allow programming during erase suspend. 4iblrd e0 x x it may be necessary to remove and restore individual block lock during erase suspend to allow programming during erase suspend. ibl 36 x x it may be necessary to restore individual block lock during erase suspend to allow programming during erase suspend. 4ibl e1 x x it may be necessary to restore individual block lock during erase suspend to allow programming during erase suspend. ibul 39 x x it may be necessary to remove individual block lock during erase suspend to allow programming during erase suspend. 4ibul e2 x x it may be necessary to remove individual block lock during erase suspend to allow programming during erase suspend. qor 6b x x read quad output (3 or 4 byte address) (1) 4qor 6c x x read quad output (4 byte address) (1) qior eb x x all array reads allowed in suspend (1) 4qior ec x x all array reads allowed in suspend (1) ddrqior ed x x all array reads allowed in suspend (1) ddr4qior ed x x all array reads allowed in suspend (1) mbr ff x x may need to reset a read operation during suspend secrp 42 x all security regions program allowed in erase suspend secrr 48 x x all security regions reads allowed in suspend table 43. commands allowed during program or erase suspend (continued) instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment document number: 002-00124 rev. *f page 100 of 158 s25fl256l/S25FL128L all command not included in table 43, commands allowed during program or erase suspend on page 98 are not allowed during erase or program suspend. the wrr, wrar, or sprp commands are not allowed during erase or program suspend, it is therefore not possible to alter the legacy block protection bits or pointer region protection during erase suspend. reading at any address within an erase-suspended sector or program-suspended page produces undetermined data. after an erase-suspended program operation is complete, the device returns to the erase-suspend mode. the system can determine the status of the program operati on by reading the wip bit in the status r egister, just as in the standard program operation. figure 88. program or erase suspend command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 89. program or erase suspend command sequence qpi mode figure 90. program or erase suspend command with continuing instruction commands sequence cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended tsl document number: 002-00124 rev. *f page 101 of 158 s25fl256l/S25FL128L 8.6.6 erase or program resume (epr 7ah) after program or read operations are completed during a program or erase suspend the erase or program resume command is sent to continue the suspended operation. after an erase or program resume command is issued, the wip bit in the status register 1 will be se t to a 1 and the suspended operation will resume if one is suspended. if there is no suspe nded program or erase operation the resume command is ignored. program or erase operations may be interr upted as often as necessary e.g. a progra m suspend command could immediately follow a program resume command but, but in order for a program or erase operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t rns . see table 63, program or erase suspend ac parameters on page 144 . the program suspend status bit in the stat us register 2 (sr2[0]) can be used to de termine if a programming operation has been suspended or was completed at the time wip ch anges to 0. the erase suspend status bit in the status register 2 (sr2[1]) can be used to determine if an erase operation has been suspende d or was completed at the time wip changes to 0. see section 6.6.2, status register 2 volatile (sr2v) on page 31 . an erase or program resume command must be written to resume a suspended operation. figure 91. erase or program resume command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 92. erase or program resume command sequence qpi mode 8.7 security regions array commands the security regions commands select which region to use by address a15 to a8 as shown below. ? security region 0: a23-16 = 00h; a1 5-8 = 00h; a7-0 = byte address ? security region 1: a23-16 = 00h; a1 5-8 = 01h; a7-0 = byte address ? security region 2: a23-16 = 00h; a1 5-8 = 02h; a7-0 = byte address ? security region 3: a23-16 = 00h; a1 5-8 = 03h; a7-0 = byte address cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction document number: 002-00124 rev. *f page 102 of 158 s25fl256l/S25FL128L 8.7.1 security region erase (secre 44h) the security region erase command erases data in the security regi on, which is in a different address space from the main array data. the security region is 1024 bytes so, the address bits for S25FL128L (a23 to a10) and s25fl256l (a24 to a10) must be zero for this command. each region can be individually erased. refer to section 6.5, security regions address space on page 26 for details on the security region. before the security region erase command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wip b it in sr1v may be checked to determine when the operation is comp leted. the e_err bit in sr2v may be checked to determine if any error occurred during the operation. the security region lock bits (cr1nv[2-5]) in the configuration register 1 can be used to protect the security regions for eras e. once a lock bit is set to 1, t he corresponding security region will be permanently locked, attempting to erase a region that is locked will fail with the e_err bit in sr2v[6] set to ?1?. when the protection register nvlock bit = ?0?, security regions 2 and 3 are protected from program or erase. attempting to eras e in a region that locked will fail with the e_err bits in sr2v[6] set to ?1?. see section 7.7.2.1, nvlock bit (pr[0]) on page 58 . the password protection mode lock bit (irp[2]) allows regions 2 and 3 to be protected from eras e operations until the correct password is provided to enable erasing of t hese security regions. attempting to erase in a region that is password locked will fail with the e_err bit in sr2v[6] set to ?1?. security region read password protection on page 59 . the protocol of the security region erase command is the same as the sector erase command. see section 8.6.1, sector erase (se 20h or 4se 21h) on page 94 for the command sequence. qpi mode is supported. 8.7.2 security region program (secrp 42h) the security region program command programs data in the security region, which is in a different address space from the main array data. the security region is 1024 bytes so, the address bits for S25FL128L (a23 to a10) and s25fl256l (a24 to a10) must be zero for this command. refer to section 6.5, security regions address space on page 26 for details on the security region. before the security region program command can be accepted by the device, a write enable (wre n) command must be issued and decoded by the device, which sets the write enable latch (wel ) in the status register to enable any write operations. the w ip bit in sr1v may be checked to determine when the operation is comp leted. the p_err bit in sr2v ma y be checked to determine if any error occurred during the operation. to program the security region array in bit granularity, the rest of the bits within a data byte can be set to ?1?. each region in the security region memory space can be progra mmed one or more times, provided that the region is not locked. however, for the best data integrity, it is recommended that one or more 16 byte length and aligned groups of bytes be programe d together and programmed only once between erase operations within each region. the security region lock bits (cr1nv[2-5]) in the configuration register 1 can be used to protect the security regions for programming. once a lock bit is set to 1, the corresponding security region will be permanently locked. attempting to program zeros or ones in a region that is locked (protected) will fail wit h the p_err bit in sr2v[5] set to ?1?. programming ones in a un- protected area does not cause an error and does not set p_err. (see configuration register 1 on page 32 for detail descriptions). when the protection register nvlock bit = ?0?, security regions 2 and 3 are protected from program or erase. attempting to program in a region that locked will fail with the p_err bit in sr2v[5] set to ?1?. see section 7.7.2.1, nvlock bit (pr[0]) on page 58 . the password protection mode lock bit (irp[2]) allows regions 2 and 3 to be protected from programming operations until the correct password is provided to enable programming of these security regions 2 and 3. attempting to program in a region that is password locked will fail with the p_err bit in sr2v[5] set to ?1?. see password protection mode on page 58 . the protocol of the security region program command is the same as the page program command. see section 8.5.1.1, page programming on page 92 for the command sequence. qpi mode is supported. document number: 002-00124 rev. *f page 103 of 158 s25fl256l/S25FL128L 8.7.3 security regions read (secrr 48h) the security region read (secrr) command provides a way to read data from the security regions. the security region is 1024 bytes so, the address bits for S25FL128L (a23 to a10) and s25fl256l (a24 to a10) must be zero for this command. refer to section 6.5, security regions address space on page 26 for details on the security regions. the instruction is followed by a 3 or 4 byte address (depending on the address length configuration cr2v[0], followed by a numbe r of latency (dummy) cycles set by cr3v[3:0]. then the selected register data are return ed. the protocol of the security region r ead command will not wrap to the starting address after the security region address is at its maxi mum; instead, the data beyond the maximum address will be undefined. the security region read comm and read latency is set by th e latency value in cr3v[3:0]. the security region read password mode enable bit (irp[6]) allows regions 3 to be protected fr om read operations until the correct password is provided to enable reading of this security region. attempting to read in region 3 that is password locked will return invalid and undefined data. see security region read password protection on page 59 . figure 93. security regions read command sequence note: 1. a = msb of address = 23 for address length cr2v[0] = 0, or 31 for cr2v[0]=1. this command is also supported in qpi mode. in qpi mode the in struction and address is shifted in and returning data out on io0 - io3. figure 94. security regions read command sequence qpi mode note: 1. a = msb of address = 23 for cr2v[0]=0, or 31 for cr2v[0]=1. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4 document number: 002-00124 rev. *f page 104 of 158 s25fl256l/S25FL128L 8.8 individual block lock commands in order to use individual block lock, the ibl protection schem e must be selected by the wps bit in configuration register 2 cr2v[2]=1. if if ibl protection scheme is not selected cr2v[2]=0 the ibl commands are ignored. individual block lock bits (ibl) are volatile, with one for each se ctor / block, and can be individually modified. by issuing t he ibl or gbl commands, a ibl bit is set to ?0? protecting each related sect or / block. by issuing the ibul or gul commands, a ibl bit is cleared to ?1? unprotecting each related se ctor or block. by issuing the iblrd comma nd the state of each ibl bit protection can be read. 8.8.1 ibl read (iblrd 3dh or 4iblrd e0h) the iblrd/4iblrd command allows reading the state of each ibl bit protection. the instruction is latched into si by the rising edge of the sck signal. the instruction is followed by the 24 or 32-bit addres s, depending on the address length configuration cr2v[0], selecting location zero within the desired sector. then the 8-bit ibl access register contents are shifted out on th e serial output so/io1. each bit is shifted out at the sck fre quency by the falling edge of the sck signal. it is possible to read the same ibl access register cont inuously by providing multiples of eight clock cycles. the address of the ibl register does not increment so this is not a means to read the entire ibl array. each loca tion must be read with a separate ibl read command. figure 95. iblrd command sequence notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command 3dh. 2. a = msb of address = 31 with command e0h. this command is also supported in qpi mode. in qpi mode the in struction and address is shifted in and returning data out on io0 - io3. figure 96. iblrd command sequence qpi notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command 3dh. 2. a = msb of address = 31 with command e0h. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles output ibl cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 instruct. address dummy ibl repeat ibl document number: 002-00124 rev. *f page 105 of 158 s25fl256l/S25FL128L 8.8.2 ibl lock (ibl 36h or 4ibl e1h) the ibl/4ibl commands sets the selected ibl bit to ?0? protecting each related sector / block. the ibl command is entered by driving cs# to the logic low state, followed by the in struction, followed by the 24 or 32-bit add ress, depending on the address length configuration cr2v[0]. the ibl co mmand affects the wip bits of the status and configuration registers in the same manner as any other programming operation. cs# must be driven to the logic high stat e after the 24 or 32-bit address (depending on the address length configuration cr2v[0 ]) has been latched in. as soon as cs# is driven to the logic high state, the self-timed ibl operat ion is initiated. while the ibl operation is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a ?1? during the self-timed ibl operati on, and is a ?0? when it is completed. figure 97. ibl command sequence notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command 36h. 2. a = msb of address = 31 with command e1h this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0-io3. figure 98. ibl command sequence qpi mode notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command 36h. 2. a = msb of address = 31 with command e1h. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address document number: 002-00124 rev. *f page 106 of 158 s25fl256l/S25FL128L 8.8.3 ibl unlock (ibul 39h or 4ibul e2h) the ibul/4ibulcommands clears the selected ibl bit to ?1? unprotecting each related sector / block. the ibul command is entered by driving cs# to the logic low state, followed by the in struction, followed by the 24 or 32-bit ad dress, depending on the address length configuration cr2v[0]. the ibul co mmand affects the wip bits of the status and configuration registers in the same manner as any other programming operation. cs# must be driven to the logic high stat e after the 24 or 32-bit address (depending on the address length configuration cr2v[0 ]) has been latched in. as soon as cs# is driven to the logic high state, the self-timed ibl opera tion is initiated. while the ibu l operation is in progress, the status regi ster may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a ?1? during the self-timed ibul operation, and is a ?0? when it is completed. figure 99. ibul command sequence notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command 39h. 2. a = msb of address = 31 with command e2h. this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0-io3. figure 100. ibul command sequence qpi mode notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command 39h. 2. a = msb of address = 31 with command e2h. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address document number: 002-00124 rev. *f page 107 of 158 s25fl256l/S25FL128L 8.8.4 global ibl lock (gbl 7eh) the gbl commands sets all the ibl bits to ?0? protecting all sectors / blocks. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the gbl. if cs# is not driven high after the last bit of instruction, the gbl operation will not be executed. as soon as cs# is driven into the logic high state, the gbl will be initiated. with the gbl in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a ?1? when the gb l is in progress and a ?0? when the gbl has been completed. figure 101. global ibl lock (gbl) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 102. global ibl lock (g bl) command sequence qpi mode 8.8.5 global ibl unlock (gbul 98h) the gbul commands clears all the ibl bits to ?1? unprotecting all sectors / blocks. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the gbul if cs# is not driven high afte r the last bit of instruction, the gbul operation will not be executed. as soon as cs# is driven into the logic high state, the gbl will be initiated. with the gbl in progress, the user can read the value of the write-in progress (wip) bit to determ ine when the operation has been completed. the wip bit will indicate a ?1? when the gb ul is in progress and a ?0? when the gbul has been completed. figure 103. global ibl un lock (gbul) command sequence cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction document number: 002-00124 rev. *f page 108 of 158 s25fl256l/S25FL128L this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 104. global ibl unlock (gbul) command sequence qpi mode 8.9 pointer region command 8.9.1 set pointer region prot ection (sprp fbh or 4sprp e3h) the sprp or 4sprp command is ignored during a suspend oper ation because the pointer value cannot be erased and re- programmed during a suspend. the sprp or 4sprp command is ignored if default power supply lock-down protection nvlock pr[0]=0 or power supply lock- down protection enabled irp[1]=0 or password protection enabled irp[2]=0 and nvlock pr[0]=0. the s25fl256l device must have 4 byte addressing enabled (cr2v[0] = 1) to set the pointer region protection register prpr (see section 6.6.10 on page 43 ) this ensures that a24 and a25 are set correctly. the S25FL128L device can have 4 byte addressing enabled (cr2v[0] = 1) or 3 byte addressing enabled (cr2v[0] = 0). before the sprp or 4sprp command can be accepted by the devic e, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will se t the write enable latch (wel) in the status register to enable any write operations. the sprp or 4sprp command is entered by driving cs# to the logic low state, followed by the instruction, followed by the 24 or 32- bit address, depending on the addre ss length configuration cr2v[0], see pointer region protection (prp) on page 54 for details on address values to select protection options. cs# must be driven to the logic high state after the last bit of address has been la tched in. if not, the sprp command is not executed. as soon as cs# is driven to the logic high state, the self-timed sprp operat ion is initiated. while the sprp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a ?1? during the self-timed sprp operation, and is a ?0? when it is completed. when the sprp oper ation is completed, the write enable latch (wel) is set to a ?0?. the sprp or 4sprp command will set the p_err or e_err bits if there is a failure in the set pointer region protection operation. for details on the address pointer defining a sector bo undary between protected and unprotected regions in the memory, see pointer region protection (prp) on page 54 . figure 105. sprp command sequence notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command fdh. 2. a = msb of address = 31 with command e3h. cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 a 1 0 instruction address document number: 002-00124 rev. *f page 109 of 158 s25fl256l/S25FL128L this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0-io3. figure 106. sprp command sequence qpi mode notes: 1. a = msb of address = 23 for address length (cr2v[0] = 0, or 31 for cr2v[0]=1 with command fdh. 2. a = msb of address = 31 with command e3h. 8.10 individual and region protection (irp) commands 8.10.1 irp register read (irprd 2bh) the irp register read instruction 2bh is shifted into si/io0 by the rising edge of the sck signal followed by one dummy cycle. this latency period allows the device?s internal circuitry enough ti me to access data at the initia l address. during latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. then the 16-bit irp register contents are shifted out on the serial outp ut s0/io1, least significant byte first. each bit is sh ifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the irp register continuously by providing mult iples of 16 clock cycles. figure 107. irprd command sequence this command is also supported in qpi mode. in qpi mode th e instruction is shifted in and returning data out on io0-io3. figure 108. irprd command sequence ? qpi mode cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction dy output irp low byte output irp high byte cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 instruct. dummy irp low byte irp high byte document number: 002-00124 rev. *f page 110 of 158 s25fl256l/S25FL128L 8.10.2 irp program (irpp 2fh) before the irp program (irpp) command can be accepted by the device, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the irpp command is entered by driving cs# to the logic low stat e, followed by the instruction and two data bytes on si, least significant byte first. the irp regist er is two data bytes in length. the irpp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# input must be driven to the logic hi gh state after the sixteenth bit of data has been latched in. if not, the irpp command is not executed. as soon as cs# is driven to t he logic high state, the self-timed irpp operat ion is initiated. wh ile the irpp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a ?1? during the self-timed irpp operation, and is a ?0? when it is completed. when the irpp operation is completed, the write en able latch (wel) is set to a ?0?. figure 109. irp program (irpp) command this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3. figure 110. irp prog ram (irpp) command qpi 8.10.3 protection regist er read (prrd a7h) the protection register read (p rrd) command allows the protection register co ntents to be read out of so/io1. the read instruction a7h is shifted into si by th e rising edge of the sck signal followed by one dummy cycle. this latency period allows the device?s internal circuitry e nough time to access data at the initial address. duri ng latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. then the 8-bit protection register contents are shifted out on the se rial output so/io1. each bit is shifted out at the sck fre quency by the falling edge of the sck signal. it is possible to read t he protection register continuousl y by providing multiples of ei ght clock cycles. the protection register contents may only be read when the de vice is in standby state wit h no other operation in progress. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input irp low byte input irp high byte cs# sclk io0 io1 io2 io3 phase 4 0 4 0 c 8 5 1 5 1 d 9 6 2 6 2 e a 7 3 7 3 f b instruct. irp low byte irp high byte document number: 002-00124 rev. *f page 111 of 158 s25fl256l/S25FL128L figure 111. protection register read (prrd) command sequence this command is also supported in qpi mode. in qpi mode th e instruction is shifted in and returning data out on io0-io3. figure 112. protection register read (prrd) command sequence ? qpi mode 8.10.4 protection regi ster lock (prl a6h) the protection register lock (prl) command clears the nvlock bi t (pr[0]) to zero and loads the irp[6] value in to secrrp (pr[6]). see section 6.6.8, protection register (pr) on page 42 . before the prl command can be accepted by the device, a write enable (wren) command must be issued and decoded by the devi ce, which sets the write enable latch (wel) in the status register to enable any write operations. the prl command is entered by driving cs# to t he logic low state, followed by the instruction. cs# must be driven to the logic high state after the eighth bit of instruction has b een latched in. if not, the prl command is not executed. as soon as cs# is driven to t he logic high state, the self-timed prl operat ion is initiated. while the prl operation is in progress, the status register may still be read to check the va lue of the write-in progress (wip) bit. the write-in progress (w ip) bit is a ?1? during the self-timed prl operation, and is a ?0? when it is completed. when the prl operation is completed, the write enable latch (wel) is set to a ?0?. figure 113. protection register lock (prl) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction dy register read repeat register read cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 instruct. dummy register read register read cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction document number: 002-00124 rev. *f page 112 of 158 s25fl256l/S25FL128L figure 114. protection register lock (prl) command sequence ? qpi mode 8.10.5 password read (passrd e7h) the correct password value may be read only after it is pr ogrammed and before the password mode has been selected by programming the password protection mode bit to 0 in the irp r egister (irp[2]). after the passwor d protection mode is selected the password is no longer readable, th e passrd command will output undefined data. the passrd command is shifted into si followed by one dummy cycle. this latency period allows t he device?s internal circuitry enough time to access data at the initial address. during late ncy cycles, the data value on are ?don?t care? and may be high impedance. then the 64-bit password is shifted out on the serial output, l east significant byte first, most significant bit of each byte f irst. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the password continuously by providing multiples of 64 clock cycles. figure 115. password read (passrd) command sequence this command is also supported in qpi mode. in qpi mode th e instruction is shifted in and returning data out on io0-io3. figure 116. password read (passrd) command sequence ? qpi mode cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 io2-io3 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction dy data 1 data 8 cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 instruct. dummy data 1 data 8 document number: 002-00124 rev. *f page 113 of 158 s25fl256l/S25FL128L 8.10.6 password program (passp e8h) before the password program (passp) comma nd can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded, the device sets the write enable latch (wel) to enabl e the passp operation. the password can only be programmed before the password mode is selected by programming th e password protection mode bit to 0 in the irp register (irp[2]). after the password protection mode is selected the passp command is ignored. the passp command is entered by driving cs# to the logic low stat e, followed by the instruction and the password data bytes on si/io0, least significant byte first, most si gnificant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic hi gh state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passp command is not executed. as soon as cs# is driven to the logic high state, the se lf-timed passp operation is init iated. while the passp operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a ?1? during the self-timed passp cycle, and is a ?0? when it is completed. the passp command can repo rt a program error in the p_err bit of the status register. when the passp operation is co mpleted, the write enable latch (wel) is set to a ?0?. figure 117. password prog ram (passp) command sequence this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3. figure 118. password program (passp) command sequence qpi mode 8.10.7 password unlock (passu eah) the passu command is entered by driving cs# to the logic low st ate, followed by the instruction and the pa ssword data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passu command is not executed. as soon as cs# is driven to the logic high state, the self-timed passu oper ation is initiated. while the passu operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a ?1? during the self-tim ed passu cycle, and is a ?0 ? when it is completed. if the passu command supplied password does not match the hidden password in the password register, an error is reported by setting the p_err bit to 1. the wip bit of the status register al so remains set to 1. it is necessary to use the clsr command t o clear the status register, the software rese t command (rsten 66h followed by rst 99h) to reset the device, or drive the reset# and io3 / reset# input to initiate a hardware reset, in order to return the p_err and wip bits to 0. this return s the device to standby state, ready for new commands such as a retry of the passu command. if the password does match, the nvlock bit is set to ?1?. cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction password byte 1 password byte 8 cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 instruct. password byte 1 password byte 8 document number: 002-00124 rev. *f page 114 of 158 s25fl256l/S25FL128L figure 119. password unlock (passu) command sequence this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3. figure 120. password unlock (passu) command sequence qpi mode 8.11 reset commands software controlled reset commands restore t he device to its initial power up state, by reloading volatile registers from non-v olatile default values. if a software reset is initiated during a erase, program or writing of a register operation the data in that se ctor, page or register is not stable, the operation that was interrupted needs to be initiated again. however, the volatile srp1 bit in the conf iguration register cr1v[0] a nd the volatile nvlock bit in the protection register are not changed by a software reset. the software reset cannot be used to circumvent the srp1 or nvlock bit protection mechanisms for the other security configuration bits. the srp1 bit and the nvlock bit will remain se t at their last value prior to the software reset. to clear the srp1 bit and set the nvlock bit to its protection mode select ed power on state, a full power-on-reset se quence or hardware reset must be done. a software reset command (rsten 66h followed by rst 99h) is executed when cs# is brought high at the end of the instruction and requires t rph time to execute. in the case of a previous power-up reset (por) failure to complete, a reset command triggers a full power up sequence requiring t pu to complete. figure 121. software / m ode bit reset command sequence cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction password byte 1 password byte 8 cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 instruct. password byte 1 password byte 8 cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction document number: 002-00124 rev. *f page 115 of 158 s25fl256l/S25FL128L this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 122. software reset / mode bit command sequence ? qpi mode 8.11.1 software reset enable (rsten 66h) the reset enable (rsten) command is required immediately befor e a software reset command (rst 99h) such that a software reset is a sequence of the two commands. any command other t han rst following the rsten command, will clear the reset enable condition and prevent a later rs t command from being recognized. 8.11.2 software reset (rst 99h) the reset (rst) command immediately following a rsten command, initiates the software rese t process. any command other than rst following the rsten command, will clear the reset e nable condition and prevent a later rst command from being recognized. 8.11.3 mode bit reset (mbr ffh) the mode bit reset (mbr) command is used to return the device from continuous high performance read mode back to normal standby awaiting any new command. because the hardware reset# input may be disabled and a device that is in a continuous high performance read mode may not recognize any normal spi command, a system hardware reset or so ftware reset command may not be recognized by the device. it is recommended to use the mbr command after a system reset when the reset# signal is not available or, before sending a software reset, to ensure the device is released from continuo us high performance read mode. the mbr command sends ones on si/io 0for eight sck cycles. io1-io3 are ?don?t care? during these cycles. 8.12 deep power down commands 8.12.1 deep power-down (dpd b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the deep po wer- down command. the lower power consumption makes the deep power-down (dpd) command especially useful for battery powered applications (see i cc1 and i cc2 in section 11.6, dc characteristics on page 132 ). the command is initiated by driving the cs# pin low and shifting the instruction code ?b9h?. the cs# pin must be driven high after the eighth bit has been latched. if this is not done the deep power-down command will not be executed. after cs# is driven high, the power-down st ate will be entered within the time duration of t dp ( table 60 on page 139 ). while in the power-down state only the release from deep power-dow n / device id command, which restores the device to normal operation, will be recognized. all other comm ands are ignored. this includes the read status register command, which is always available during normal operation. ignoring all but one command also makes the power down state a useful condition for securing maximum write protection. while in the deep power-down mode the device will only accept a hardware reset which will initiate a power on reset that will restore the device to normal operation. the device always po wers-up in the normal operatio n with the standby current of i cc1 . cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction document number: 002-00124 rev. *f page 116 of 158 s25fl256l/S25FL128L figure 123. deep power down (dpd) command sequence this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 124. deep power down (dpd) command sequence ? qpi mode 8.12.2 release from deep power- down / device id (res abh) the release from deep power-down /device id command is a mult i-purpose command. it can be used to release the device from the deep power-down state, or obtain the de vices electronic identif ication (id) number. to release the device from the deep power-down state, the command is issued by driving the cs# pin low, shifting the instructio n code ?abh? and driving cs# high. release from deep power-down will take the time duration of t res ( table 60 on page 139 ) before the device will resume normal operation and other commands ar e accepted. the cs# pin must remain high during the t res time duration. when used only to obtain the device id while not in the deep po wer-down state, the command is in itiated by driving the cs# pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling e dge of clk with most significant bit (msb) first. the device id values for the s25fl-l family is listed in and table 50, manufacturer device type on page 127 . continued shifting of output beyond the end of t he defined id address space will provide undefined data. the command is completed by driving cs# high. when used to release the device from the deep power-down st ate and obtain the device id, the command is the same as previously described, and shown in figure 127 and figure 128 , except that after cs# is driven high it must remain high for a time duration of t res . after this time duration the device will resume normal operation and other commands will be accepted. if the release from deep power-down / device id command is issued while an erase, program or write cycle is in process (when busy equals 1) the command is ignored and will not have any effects on the current cycle. figure 125. release from deep power down (res) command sequence cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 instruction document number: 002-00124 rev. *f page 117 of 158 s25fl256l/S25FL128L this command is also supported in qpi mode. in qp i mode the instruction is shifted in on io0-io3. figure 126. release from deep power down (res) command sequence ? qpi mode figure 127. read identification (res) command sequence this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3. figure 128. read identification (res) qpi mode command cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si_io0 so_io1 phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 7 1 0 instruction dummy dev id dev id cs# sclk io0 io1 io2 io3 phase 4 0 23 22 4 0 4 0 4 0 4 5 1 5 5 1 5 1 5 6 2 6 6 2 6 2 6 7 3 7 7 3 7 3 7 instruction dummy dev id dev id document number: 002-00124 rev. *f page 118 of 158 s25fl256l/S25FL128L 9. data integrity 9.1 erase endurance note: 1. each write command to a non-volatile register causes a p/e cycle on the entire non-volatile register array. 9.2 data retention contact cypress sales or an fae representative for additional inform ation regarding data integrity. table 44. erase endurance parameter min unit program/erase cycles per main flash array sectors 100k p/e cycle program/erase cycles per security regist ers or non-volatile register array (1) 1k p/e cycle table 45. data retention parameter test conditions minimum time unit data retention time 10k program/erase cycles 20 years 100k program/erase cycles 2 years document number: 002-00124 rev. *f page 119 of 158 s25fl256l/S25FL128L 10. software inter face reference 10.1 jedec jesd216b serial fl ash discoverable parameters this document defines the serial flash discoverable parameters (s fdp) revision b data structure used in the following cypress serial flash devices: ? s25fl-l family these data structure values are an update to the earlier revision sfdp data structur e currently existing in the above devices. the read sfdp (rsfdp) command (5ah) reads information from a se parate flash memory address space for device identification, feature, and configuration information, in accord with the je dec jesd216b standard for serial flash discoverable parameters. the sfdp data structure consists of a he ader table that identifies the revision of the jesd216 header format that is supported and provides a revision number and pointer for each of the sfdp paramet er tables that are provided. the parameter tables follow the sfdp header. however, the parameter tables may be placed in any physical location and order within the sfdp address space. the tables are not necessarily adjacent nor in the same order as their header table entries. the sfdp header points to the following parameter tables: ? basic flash ? this is the original sfdp table. it has a few modified fields and new additional field added at the end of the table. ? 4 byte address instruction ? this is the original sfdp table. it has a few modified fields and new additional field added at the end of the table. the physical order of the tables in the sfdp address space is: sfdp header, basic flash sector map, 4 byte instruction. the sfdp address space is programmed by cypress and read-only for the host system. 10.1.1 serial flash discoverable parameters (sfdp) address map the sfdp address space has a header starting at address zero that identifies the sfdp data stru cture and provides a pointer to each parameter. one basic flash parameter is mandated by the jedec jesd216b standard . optional parameter tables for 4 byte address instructions follow the basic flash table. table 46. sfdp overview map byte address description 0000h location zero within jedec jesd216b sfdp space - start of sfdp header ,,, remainder of sfdp header followed by undefined space 0300h start of sfdp parameter ... remainder of sfdp jedec parameter followed by undefined space document number: 002-00124 rev. *f page 120 of 158 s25fl256l/S25FL128L 10.1.2 sfdp header field definitions table 47. sfdp header sfdp byte address sfdp dword name data description 00h sfdp header 1st dword 53h this is the entry point for read sfdp (5ah) command i.e. location zero within sfdp space ascii ?s? 01h 46h ascii ?f? 02h 44h ascii ?d? 03h 50h ascii ?p? 04h sfdp header 2nd dword 06h sfdp minor revision (06h = jedec jesd216 revision b) - this revision is backward compatible wi th all prior minor revisions. sfdp reading and parsing software will work with higher minor revision numbers than the software was designed to handle. software designed for a higher revisions must know how to handle earlier revisions. example: sfdp reading and parsing software for minor revision 0 will still work with minor revision 6. sfdp reading and parsing software for minor revision 6 must be designed to also read minor revision 0 or 5. do not do a simple compare on the minor revision number, looking only for a match with the revision number that the soft ware is designed to handle. there is no problem with using a higher number minor revision. 05h 01h sfdp major revision this is the original major revision. this major revision is compatible with all sfdp reading and parsing software. 06h 01h number of parameter headers (zero based, 01h = 2 parameters) 07h ffh unused 08h parameter header 0 1st dword 00h parameter id lsb (00h = jede c sfdp basic spi flash parameter) 09h 06h parameter minor revision (06h = jesd216 revision b) 0ah 01h parameter major revision (01h = the original major revisi on - all sfdp software is compatible with this major revision. 0bh 10h parameter table length (in double words = dwords = 4 byte units) 10h = 16 dwords 0ch parameter header 0 2nd dword 00h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 0300h address 0dh 03h parameter table pointer byte 1 0eh 00h parameter table pointer byte 2 0fh ffh parameter id msb (ffh = jedec defined parameter) 10h parameter header 1 1st dword 84h parameter id lsb (84h = sfdp 4 byte address instructions parameter) 11h 00h parameter minor revision (00h = initial version as defined in jesd216 revision b) 12h 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 13h 02h parameter table length (in double words = dwords = 4 byte units) (2h = 2 dwords) 14h parameter header 1 2nd dword 40h parameter table pointer byte 0 (dword = 4 byte aligned) jedec parameter byte offset = 0340h 15h 03h parameter table pointer byte 1 16h 00h parameter table pointer byte 2 17h ffh parameter id msb (ffh = jedec defined parameter) document number: 002-00124 rev. *f page 121 of 158 s25fl256l/S25FL128L 10.1.3 jedec sfdp basic spi flash parameter table 48. basic spi flash parameter, jedec sfdp rev b sfdp parameter relative byte address sfdp dword name data description 00h jedec basic flash parameter dword-1 e5h start of sfdp jedec parameter bits 7:5 = unused = 111b bit 4:3 = 05h is volatile status register wr ite instruction and status register is default non-volatile= 00b bit 2 = program buffer > 64bytes = 1 bits 1:0 = uniform 4kb erase is supported through out the device = 01b 01h 20h bits 15:8 = uniform 4kb erase instruction = 20h 02h fbh bit 23 = unused = 1b bit 22 = supports qor (1-1-4) read, yes = 1b bit 21 = supports qio (1-4-4) read, yes =1b bit 20 = supports dio (1-2-2) read, yes = 1b bit19 = supports ddr, yes = 1b bit 18:17 = number of address bytes, 3 or 4 = 01b bit 16 = supports fast read sio and dio yes = 1b 03h ffh bits 31:24 = unused = ffh 04h jedec basic flash parameter dword-2 ffh density in bits, zero based, 128mb = 07ffffffh256mb = 0fffffffh512mb = 1fffffffh 05h ffh 06h ffh 07h 07h 128mb0fh 256mb1fh 512mb 08h jedec basic flash parameter dword-3 48h bits 7:5 = number of qio mode cycles = 010b bits 4:0 = number of fast read qio dummy cycles = 01000b for default latency code 09h ebh fast read qio instruction code 0ah 08h bits 23:21 = number of quad out mode cycles = 000b bits 20:16 = number of quad out dummy cycles = 01000b for default latency code 0bh 6bh quad out instruction code 0ch jedec basic flash parameter dword-4 08h bits 7:5 = number of dual out mode cycles = 000b bits 4:0 = number of dual out dummy cycles = 01000b for default latency code 0dh 3bh dual out instruction code 0eh 88 h bits 23:21 = number of dual i/o mode cycles = 100b bits 20:16 = number of dual i/o dummy cycles = 01000b for default latency code 0fh bbh dual i/o instruction code 10h jedec basic flash parameter dword-5 feh bits 7:5 rfu = 111b bit 4 = qpi supported = 1b bits 3:1 rfu = 111b bit 0 = dual all not supported = 0b 11h ffh bits 15:8 = rfu = ffh 12h ffh bits 23:16 = rfu = ffh 13h ffh bits 31:24 = rfu = ffh 14h jedec basic flash parameter dword-6 ffh bits 7:0 = rfu = ffh 15h ffh bits 15:8 = rfu = ffh 16h ffh bits 23:21 = number of dual all mode cycles = 111b bits 20:16 = number of dual all dummy cycles = 11111b 17h ffh dual all instruction code 18h jedec basic flash parameter dword-7 ffh bits 7:0 = rfu = ffh 19h ffh bits 15:8 = rfu = ffh 1ah 48h bits 23:21 = number of qpi mode cycles = 010b bits 20:16 = number of qpi dummy cy cles = 01000b for default latency code 1bh ebh qpi fast read instruction code (same as qio when qpi is enabled) document number: 002-00124 rev. *f page 122 of 158 s25fl256l/S25FL128L 1ch jedec basic flash parameter dword-8 0ch sector type 1 size 2^n bytes = 4kb = 0ch (for uniform 4kb) 1dh 20h sector type 1 instruction 1eh 0fh sector type 2 size 2^n bytes = 32kb = 0fh (for uniform 32kb) 1fh 52h sector type 2 instruction 20h jedec basic flash parameter dword-9 10h sector type 3 size 2^n bytes = 64kb = 10h (for uniform 64kb) 21h d8h sector type 3 instruction 22h 00h sector type 4 size 2^n bytes = not supported = 00h 23h ffh sector type 4 instruction = not supported = ffh 24h jedec basic flash parameter dword- 10 21h bits 31:30 = sector type 4 erase, typica l time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = rfu = 11b bits 29:25 = sector type 4 erase, typical ti me count = rfu = 1_1111b (typ erase time = count +1 * units = rfu =11111) bits 24:23 = sector type 3 erase, typica l time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 22:18 = sector type 3 erase, typica l time count = 1_0000b (typ erase time = count +1 * units = 17*16ms = 272ms) bits 17:16 = sector type 2 erase, typica l time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 15:11 = sector type 2 erase, typical time count = 0_1011b (typ erase time = count +1 * units = 12*16ms = 192ms) bits 10:9 = sector type 1 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 8:4 = sector type 1 erase, typical time count = 0_0010b (typ erase time = count +1 * units = 3*16ms = 48ms) bits 3:0 = count = (max erase time / (2 * typical erase time))- 1 = 0001b multiplier from typical erase time to maximum erase time = 4x multiplier max erase time = 2*(count +1)*typ erase time binary fields: 11-11111-01-10000-01-01011-01-00010-0001 nibble format: 1111_1110_1100_0001_0101_1010_0010_0001 hex format: fe_c1_5a_21 25h 5ah 26h c1h 27h feh 28h jedec basic flash parameter dword- 11 81h bits 23 = byte program typical time, addi tional byte units (0b: 1us, 1b:8us) = 1us = 0b bits 22:19 = byte program typical time, addi tional byte count, (count+1)*units, count = 0101b, (typ program time = count +1 * units = 6*1us =6us bits 18 = byte program typi cal time, first byte units (0b:1us, 1b:8us) = 1us = 0b bits 17:14 = byte program typical time, fi rst byte count, (count+1)*units, count = 0111b, (typ program time = count +1 * units = 8*1us = 8us bits 13 = page program typical time units (0b:8us, 1b:64us) = 64us = 1b bits 12:8 = page program typical time c ount, (count+1)*units, count = 00100b, (typ program time = count +1 * units = 5*64us = 320us) bits 7:4 = n = 1000b, page size= 2^n = 256b page bits 3:0 = count = 0001b = (max page program time / (2 * typ page program time))- 1 multiplier from typical page program time to maximum page program time = 4x multiplier max page program time = 2*(count +1)*typ page program time binary fields: 0-0101-0-0111-1-00100-1000-0001 nibble format: 0010_1001_1110_0100_1000_0001 hex format: 29_74_81 29h e4h 2ah 29h 2bh d1h 128mb e2h 256mb 128mb = 1101_0001b = d1h bit 31 reserved = 1b bits 30:29 = chip erase, typical time unit s (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b bits 28:24 = chip erase, typical time c ount, (count+1)*units, count = 10001b, (typ program time = count +1 * units = 18*4s = 72s 256mb = 1110_0010b = e2h bit 31 reserved = 1b bits 30:29 = chip erase, typical time unit s (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 64s = 11b bits 28:24 = chip erase, typical time c ount, (count+1)*units, count = 00010b, (typ program time = count +1 * units = 3*64s = 192s table 48. basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description document number: 002-00124 rev. *f page 123 of 158 s25fl256l/S25FL128L 2ch jedec basic flash parameter dword- 12 cch bit 31 = suspend and resume supported = 0b bits 30:29 = suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 8us= 10b bits 28:24 = suspend in-progress erase max latency count = 00100b, max erase suspend latency = count +1 * units = 5*8us = 40us bits 23:20 = erase resume to suspend interv al count = 0001b, interval = count +1 * 64us = 2 * 64us = 128us bits 19:18 = suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 8us= 10b bits 17:13 = suspend in-progress program max latency count = 00100b, max erase suspend latency = count +1 * units = 5*8us = 40us bits 12:9 = program resume to suspend inte rval count = 0001b, interval = count +1 * 64us = 2 * 64us = 128us bit 8 = rfu = 1b bits 7:4 = prohibited operat ions during erase suspend = xxx0b: may not initiate a new eras e anywhere (erase nesting not permitted) + xx0xb: may not initiate a page program anywhere + x1xxb: may not initiate a read in the erase suspended sector size + 1xxxb: the erase and program restri ctions in bits 5:4 are sufficient = 1100b bits 3:0 = prohibited operat ions during program suspend = xxx0b: may not initiate a new eras e anywhere (erase nesting not permitted) + xx0xb: may not initiate a new page program anywhere (program nesting not permitted) + x1xxb: may not initiate a read in the program suspended page size + 1xxxb: the erase and program restri ctions in bits 1:0 are sufficient = 1100b binary fields: 0-10-00100-0001-10-00100-0001-1-1100-1100 nibble format: 0100_0100_0001_1000_1000_0011_1100_1100 hex format: 44_18_83_cc 2dh 83h 2eh 18h 2fh 44h 30h jedec basic flash parameter dword- 13 7ah bits 31:24 = erase suspend instruction = 75h bits 23:16 = erase resume instruction = 7ah bits 15:8 = program suspend instruction = 75h bits 7:0 = program resume instruction = 7ah 31h 75h 32h 7ah 33h 75h 34h jedec basic flash parameter dword- 14 f7h bit 31 = deep power down supported = supported = 0 bits 30:23 = enter deep power down instruction = b9h = 1011_1001b bits 22:15 = exit deep power down instruction = abh = 1010_1011b bits 14:13 = exit deep power down to nex t operation delay units = (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 1us = 01b bits 12:8 = exit deep power down to nex t operation delay count = 00010b, exit deep power down to next operation delay = (count+1)*units = 3*1us=3us bits 7:4 = rfu = fh bit 3:2 = status register polling device busy = 01b: legacy status polling supported = us e legacy polling by reading the status register with 05h instruction and c hecking wip bit[0] (0=ready; 1=busy). bits 1:0 = rfu = 11b binary fields: 0-10111001-10101011-01-00010-1111-01-11 nibble format: 0101_1100_1101_0101_1010_0010_1111_0111 hex format: 5c_d5_a2_f7 35h a2h 36h d5h 37h 5ch table 48. basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description document number: 002-00124 rev. *f page 124 of 158 s25fl256l/S25FL128L 38h jedec basic flash parameter dword- 15 22h bits 31:24 = rfu = ffh bit 23 = hold and wp disable = not supported = 0b bits 22:20 = quad enable requirements = 101b: qe is bit 1 of the status register 2. status register 1 is read using read status instruction 05h. status register 2 is read using instruction 35h. qe is set via write status instruction 01h with two data bytes wher e bit 1 of the second byte is one. it is cleared via write status with two data bytes where bit 1 of the second byte is zero. bits 19:16 0-4-4 mode entry method = xxx1b: mode bits[7:0] = a5h note: qe must be set prior to using this mode + x1xxb: mode bits[7:0] = axh + 1xxxb: rfu = 1101b bits 15:10 0-4-4 mode exit method = xx_xxx1b: mode bits[7:0] = 00h will term inate this mode at the end of the current read operation + xx_1xxxb: input fh (mode bit reset) on dq0- dq3 for 8 clocks. this will terminate the mode prior to the next read operation. + 11_x1xx: rfu = 111101 bit 9 = 0-4-4 mode supported = 1 bits 8:4 = 4-4-4 mode enable sequences = 0_0010b: issue instruction 38h bits 3:0 = 4-4-4 mode disable sequences = 0010b: 4-4-4 issues f5h instruction binary fields: 11111111-0- 101-1101- 111101-1- 00010-0010 nibble format: 1111_1111_0101_1101_1111_0110_0010_0010 hex format: ff_5d_f6_22 39h f6h 3ah 5dh 3bh ffh table 48. basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description document number: 002-00124 rev. *f page 125 of 158 s25fl256l/S25FL128L 3ch jedec basic flash parameter dword- 16 e8h bits 31:24 = enter 4-byte addressing = xxxx_xxx1b:issue instru ction b7 (preceding write enable not required = xxxx_1xxxb: 8-bit volatile bank register us ed to define a[30:24] bits. msb (bit[7]) is used to enable/disable 4-byte address mode. when msb is set to ?1?, 4-byte address mode is active and a[30:24] bits are don?t care. read with instruction 16h. write instruction is 17h with 1 byte of data. when msb is cleared to ?0?, select the active 128 mb segment by setting the appropriate a[30:24] bits and use 3-byte addressing. + xx1x_xxxxb: supports dedicated 4-byte addr ess instruction set. consult vendor data sheet for the instruction set definition or look for 4 byte address parameter table. + 1xxx_xxxxb: reserved = 10100001b bits 23:14 = exit 4-byte addressing = xx_xxxx_xxx1b:iss ue instruction e9h to exit 4-byte address mode (write enable instruction 06h is not required) = xx_xxxx_1xxxb: 8-bit volatile bank register used to defi ne a[30:24] bits. msb (bit[7]) is used to enable/disable 4-by te address mode. when msb is cleared to ?0?, 3-byte address mode is active and a30:a24 are used to select the active 128 mb memory segment. read with instruction 16h. write in struction is 17h, data length is 1 byte. + xx_xx1x_xxxxb: hardware reset + xx_x1xx_xxxxb: software reset (see bits 13:8 in this dword) + xx_1xxx_xxxxb: power cycle + x1_xxxx_xxxxb: reserved + 1x_xxxx_xxxxb: reserved = 1111100001b bits 13:8 = soft reset and rescue sequence support = x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. the reset enable, reset sequence may be iss ued on 1,2, or 4 wires depending on the device operating mode = 010000b bit 7 = rfu = 1 bits 6:0 = volatile or non-volatile regist er and write enable instruction for status register 1 = xxx_1xxxb: non-volatile/volatile status r egister 1 powers-up to last written value in the non-volatile status register, use instruct ion 06h to enable write to non-volatile status register. volatile status register may be activated after power-up to override the non- volatile status register, use instruction 50h to enable write and activate the volatile status register. + x1x_xxxxb: reserved + 1xx_xxxxb: reserved = 1101000b binary fields: 10100001- 1111 100001-010000-1-1101000 nibble format: 1010_0001_1111_1000_0101_0000_1110_1000 hex format: a1_f8_60_e8 3dh 50h 3eh f8h 3fh a1h table 48. basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description document number: 002-00124 rev. *f page 126 of 158 s25fl256l/S25FL128L 10.1.4 jedec sfdp 4-byte address instruction table table 49. 4-byte address instruction, jedec sfdp rev b sfdp parameter relative byte address sfdp dword name data description 40h jedec 4 byte address instructions parameter dword- 1h fbh supported = 1, not supported = 0 bits 31:20 = rfu = fffh bit 19 = support for non-volatile indi vidual sector lock write command, instruction=e3h = 0 bit 18 = support for non-volatile individual sector lock read command, instruction=e2h = 0 bit 17 = support for volatile individual sector lock write command, instruction=e1h = 1 bit 16 = support for volatile individual sector lock read command, instruction=e0h = 1 bit 15 = support for (1-4-4) dtr_read command, instruction = eeh = 1 bit 14 = support for (1-2-2) dtr_read command, instruction = beh = 0 bit 13 = support for (1-1-1) dtr_read command, instruction = 0eh = 0 bit 12 = support for erase command ? type 4 = 0 bit 11 = support for erase command ? type 3 = 1 bit 10 = support for erase command ? type 2 = 1 bit 9 = support for erase command ? type 1 = 1 bit 8 = support for (1-4-4) page program command, instruction = 3eh =0 bit 7 = support for (1-1-4) page program command, instruction = 34h = 1 bit 6 = support for (1-1-1) page program command, instruction = 12h = 1 bit 5 = support for (1-4-4) fast_read command, instruction = ech = 1 bit 4 = support for (1-1-4) fast_read command, instruction = 6ch = 1 bit 3 = support for (1-2-2) fast_read command, instruction = bch = 1 bit 2 = support for (1-1-2) fast_read command, instruction = 3ch = 0 bit 1 = support for (1-1-1) fast_read command, instruction = 0ch = 1 bit 0 = support for (1-1-1) read command, instruction = 13h = 1 nibble format: 1111_1111_1111_0011_1000_1110_1111_1011 hex format: ff_f3_8e_fb 41h 8eh 42h f3h 43h ffh 44h jedec 4 byte address instructions parameter dword- 2h 21h bits 31:24 = ffh = instruction for erase type 4: rfu bits 23:16 = dch = instruction for erase type 3 block bits 15:8 = 52h = instruction for erase type 2 half block bits 7:0 = 21h = instruction for erase type 1 sector 45h 52h 46h dch 47h ffh document number: 002-00124 rev. *f page 127 of 158 s25fl256l/S25FL128L 10.2 device id address map 10.2.1 field definitions 10.3 initial delivery state the device is shipped from cypress with non-volatile bits set as follows: ? the entire memory array is erased: i.e. all bi ts are set to 1 (each byte contains ffh). ? the security region address space has all bytes erased to ffh. ? the sfdp address space contains the values as defined in the description of the sfdp address space. ? the id address space contains the values as def ined in the description of the id address space. ? the status register 1 non-volatile contains 00h (all sr1nv bits are cleared to 0?s). ? the configuration register 1 non-volatile contains 00h. ? the configuration register 2 non-volatile contains 60h. ? the configuration register 3 non-volatile contains 78h. ? the password register contains ffffffff-ffffffffh ? the irp register bits are fffdh for standard part and ffffh for high security part. ? the prpr register bits are ffffffh table 50. manufacturer device type byte address data description 00h 01h manufacturer id for cypress 01h 60h device id most significant byte - memory interface type 02h 18h (128mb) 19h (256mb) device id least significant byte - density and features 03h undefined reserved for future use table 51. unique device id byte address data description 00h to 07 8 byte unique device id 64-bit unique id number, see section section 6.3.1 , device unique id on page 26 08h to 0f additional 8 byte unique device id additional bytes for 128-bit unique id number 10 to 1fh undefined rese rved for future use 20h to 37h 24 bytes oem name for oem name document number: 002-00124 rev. *f page 128 of 158 s25fl256l/S25FL128L 11. electrical specifications 11.1 absolute maximum ratings (note 3) storage temperature plastic packages........................................................................................... ..........................?65c to +150c ambient temperature with power appl ied......................................................................................... .............. ..........?65c to +125c v cc ............................................................................................................................... ................................................?0.5 v to +4.0 v input voltage with respect to ground (vss) (note 1)... .............. .............. ........... ............ ........... ........... ...............?0.5 v to v cc + 0.5 v output short circuit current (note 2).................... ...................................................................... ............................................ 100 ma notes: 1. see section 11.4.3, input signal overshoot on page 129 for allowed maximums during signal transition. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the dev ice. this is a stress ratin g only; functional operation of the device at these or any other condi tions above those indicated in the operational sect ions of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 11.2 latchup characteristics note: 1. excludes power supply v cc . test conditions: v cc = 3.0 v, one connection at a time tested, connections not being tested are at v ss . 11.3 thermal resistance table 52. latchup specification description min max unit input voltage with respect to v ss on all input only connections ?1.0 v cc + 1.0 v input voltage with respect to v ss on all i/o connections ?1.0 v cc + 1.0 v v cc current ?100 +100 ma table 53. thermal resistance parameter description so316 soc008 wnd008 wng008 fab024 fac024 unit theta ja thermal resistance (junction to ambient) 3853.2732183939c/w document number: 002-00124 rev. *f page 129 of 158 s25fl256l/S25FL128L 11.4 operating ranges operating ranges define those limit s between which the functionalit y of the device is guaranteed. 11.4.1 power supply voltages 11.4.2 temperature ranges 11.4.3 input signal overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v cc . during voltage transitions, inputs or i/os may overshoot v ss to ? 1.0 v or overshoot to v cc +1.0 v, for periods up to 20 ns. figure 129. maximum ne gative overshoot waveform figure 130. maximum positive overshoot waveform v cc 2.7v to 3.6v parameter symbol devices spec unit min max ambient temperature t a industrial (i) ?40 +85 c industrial plus (v) ?40 +105 extended (n) ?40 +125 automotive, aec-q100 grade 3 (a) ?40 +85 automotive, aec-q100 grade 2 (b) ?40 +105 automotive, aec-q100 grade 1 (m) ?40 +125 v ss to v cc ? 1.0 v < = 20 ns v cc + 1.0 v < = 20 ns v ss to v cc document number: 002-00124 rev. *f page 130 of 158 s25fl256l/S25FL128L 11.5 power-up and power-down the device must not be selected at power-up or power- down (that is, cs# must follo w the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu ? v ss at power-down user is not allowed to enter any command until a valid delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 131 . however, correct operation of the device is not guaranteed if v cc returns below v cc (min) during t pu . no command should be sent to the device until the end of t pu . the device draws i por during t pu . after power-up (t pu ), the device is in standby mode, draws cmos standby current (i sb ), and the wel bit is reset. during power-down or if supply voltage drops below v cc (cut-off), the supply voltage must stay below v cc (low) for a period of t pd for the part to initialize correctly on power-up. see figure 132 on page 131 . if during a voltage drop the v cc stays above v cc (cut-off) the part will stay initialized and will work correctly when v cc is again above v cc (min). in the event power-on reset (por) did not complete correctly after power up , the assertion of the reset# sign al or receiving a software re set command (rst en 66h followed by rst 99h) will restart the por process. if v cc drops below the v cc (cut-off) during an embedded program or erase operation the embedded o peration may be aborted and the data in that memory area may be incorrect. normal precautions must be taken for supply rail decoupling to stabilize the v cc supply at the device. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the pa ckage supply connection (this ca pacitor is generally of the order of 0.1 f). figure 131. power-up table 54. power-up / power-down voltage and timing symbol parameter min max unit v cc (min) v cc (minimum operation voltage) 2.7 ? v v cc (cut-off) v cc (cut 0ff where re-initialization is needed) 2.4 ? v v cc (low) v cc (low voltage for initialization to occur) 1.0 ? v t pu v cc (min) to read operation ? 300 s t pd v cc (low) time 10.0 ? s tpu full device access v cc (min) v cc (max) time document number: 002-00124 rev. *f page 131 of 158 s25fl256l/S25FL128L figure 132. power-down and voltage drop v cc (max) v cc (min) v cc (cut-off) v cc (low) tpu no device access allowed tpd time document number: 002-00124 rev. *f page 132 of 158 s25fl256l/S25FL128L 11.6 dc characteristics notes: 1. typical values are at t ai = 25 c and v cc = 3.0 v. 2. outputs unconnected during read data return. output switching current is not included. table 55. dc characteristics ? operating temperature range ?40c to +85c symbol parameter test conditions min typ (1) max unit v il input low voltage ? ?0.5 ? 0.3 ? v cc v v ih input high voltage ? 0.7 ? v cc ?v cc +0.4 v v ol output low voltage i ol = 0.1 ma, v cc =v cc min ? 0.2 v v oh output high voltage i oh = ?0.1 ma v cc - 0.2 ? v i li input leakage current v cc =v cc max, v in =v ih or v ss , cs# = v ih ? ? 2 a i lo output leakage current v cc =v cc max, v in =v ih or v ss , cs# = v ih ? ?2a i cc1 active power supply current (read) (2) serial sdr@5 mhz serial sdr@10mhz serial sdr@20 mhz serial sdr@50 mhz serial sdr@108mhz serial sdr@133mhz qio/qpi sdr@108mhz qio/qpi sdr@133 mhz qio/qpi ddr@30mhz qio/qpi ddr@66 mhz ? 10 10 10 15 25 30 25 30 15 30 15 15 15 20 30 35 30 35 20 35 ma i cc2 active power supply current (page program) cs#=v cc ?4050ma i cc3 active power supply current (wrr or wrar) cs#=v cc ?4050ma i cc4 active power supply current (se) cs#=v cc ?4050ma i cc5 active power supply current (hbe, be) cs#=v cc ?4050ma i sb standby current reset#, cs#=v cc ; si, sck = v cc or v ss : spi, dual i/o and quad i/o modes ?2035a reset#, cs#=v cc ; si, sck = v cc or v ss : qpi mode ? 60 100 a i dpd deep power down current reset#, cs# = v cc , v in = gnd or v cc ? 2 20 a i por power on reset current reset#, cs#=v cc ; si, sck = v cc or v ss ?1530ma document number: 002-00124 rev. *f page 133 of 158 s25fl256l/S25FL128L notes: 1. typical values are at t ai = 25 c and v cc = 3.0 v. 2. outputs unconnected during read data return. output switching current is not included. table 56. dc characteristics ? operating temperature range ?40c to +105c symbol parameter test conditions min typ (1) max unit v il input low voltage ? ?0.5 ? 0.3 ? v cc v v ih input high voltage ? 0.7 ? v cc ?v cc +0.4 v v ol output low voltage i ol = 0.1 ma, v cc =v cc min ? ? 0.2 v v oh output high voltage i oh = ?0.1 ma v cc - 0.2 ? ? v i li input leakage current v cc =v cc max, v in =v ih or v ss , cs# = v ih ? ?4 a i lo output leakage current v cc =v cc max, v in =v ih or v ss , cs# = v ih ? ?4 a i cc1 active power supply current (read) (2) serial sdr@5 mhz serial sdr@10mhz serial sdr@20 mhz serial sdr@50 mhz serial sdr@108mhz serial sdr@133mhz qio/qpi sdr@108mhz qio/qpi sdr@133 mhz qio/qpi ddr@30mhz qio/qpi ddr@66 mhz ? 10 10 10 15 25 30 25 30 15 30 20 20 20 25 35 40 35 40 25 40 ma i cc2 active power supply current (page program) cs#=v cc ?4060ma i cc3 active power supply current (wrr or wrar) cs#=v cc ?4060ma i cc4 active power supply current (se) cs#=v cc ?4060ma i cc5 active power supply current (hbe, be) cs#=v cc ?4060ma i sb standby current reset#, cs#=v cc ; si, sck = v cc or v ss : spi, dual i/o and quad i/o modes ?2045a reset#, cs#=v cc ; si, sck = v cc or v ss : qpi mode ?60110a i dpd deep power down current reset#, cs# = v cc , v in = gnd or v cc ?230a i por power on reset current reset#, cs#=v cc ; si, sck = v cc or v ss ?1530ma document number: 002-00124 rev. *f page 134 of 158 s25fl256l/S25FL128L notes: 1. typical values are at t ai = 25 c and v cc = 1.8 v. 2. outputs unconnected during read data return. output switching current is not included. 11.6.1 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, erase, and write operations have complete d. the device then goes into t he standby power mode, and powe r consumption drops to i sb . 11.6.2 deep power down power mode (dpd) the deep power down mode is enabled by inputing the command instruction code ?b9h? and the power consumption drops to i dpd . in dpd mode the device responds only to the resume from dpd command (res abh ) or hardware reset (reset# and io3 / reset#). all other commands are ignored during dpd mode. table 11.5 dc characteristics ? operating temperature range ?40c to +125c symbol parameter test conditions min typ (1) max unit v il input low voltage ? ?0.5 ? 0.3 ? v cc v v ih input high voltage ? 0.7 ? v cc ?v cc +0.4 v v ol output low voltage i ol = 0.1 ma, v cc =v cc min ? ? 0.2 v v oh output high voltage i oh = ?0.1 ma v cc - 0.2 ? ? v i li input leakage current v cc =v cc max, v in =v ih or v ss , cs# = v ih ? ?4 a i lo output leakage current v cc =v cc max, v in =v ih or v ss , cs# = v ih ? ?4 a i cc1 active power supply current (read) (2) serial sdr@5 mhz serial sdr@10mhz serial sdr@20 mhz serial sdr@50 mhz serial sdr@108mhz serial sdr@133mhz qio/qpi sdr@108mhz qio/qpi sdr@133 mhz qio/qpi ddr@30mhz qio/qpi ddr@66 mhz ? 10 10 10 15 25 30 25 30 15 30 30 30 30 35 45 50 45 50 35 50 ma i cc2 active power supply current (page program) cs#=v cc ?4070ma i cc3 active power supply current (wrr or wrar) cs#=v cc ?4070ma i cc4 active power supply current (se) cs#=v cc ?4070ma i cc5 active power supply current (hbe, be) cs#=v cc ?4070ma i sb standby current reset#, cs#=v cc ; si, sck = v cc or v ss : spi, dual i/o and quad i/o modes ?2075a reset#, cs#=v cc ; si, sck = v cc or v ss : qpi mode ? 60 150 a i dpd deep power down current reset#, cs# = v cc , v in = gnd or v cc ?250a i por power on reset current reset#, cs#=v cc ; si, sck = v cc or v ss ?1535ma document number: 002-00124 rev. *f page 135 of 158 s25fl256l/S25FL128L 12. timing specifications 12.1 key to switching waveforms figure 133. waveform element meanings 12.2 ac test conditions figure 134. test setup notes 1. load capacitance depends on the operation frequency or mode of operation. 2. ac characteristics tables assume clock and da ta signals have the same slew rate (slope). sdr ac characteristics on page 139 note 6 for slew rates at operating frequency's. figure 135. input, output, and timing reference levels table 57. ac measurement conditions symbol parameter min max unit c l load capacitance ? 15 / 30 (1) pf ? input pulse voltage 0.2 ? v cc 0.8 v cc v ? input timing ref voltage 0.5 v cc v ? output timing ref voltage 0.5 v cc v input symbol output valid at logic high or low valid at logic high or low high impedance any change permitted logic high logic low valid at logic high or low valid at logic high or low high impedance changing, state unknown logic high logic low device under te s t c l v cc + 0.4v 0.8 x v cc 0.2 x v cc - 0.5v timing reference level 0.5 x v cc v cc - 0.2v 0.2v input levels output levels document number: 002-00124 rev. *f page 136 of 158 s25fl256l/S25FL128L 12.2.1 capacitance characteristics 12.3 reset if a hardware reset is initiated during a erase, program or writin g of a register operation the da ta in that sector, page or re gister is not stable, the operation that was interr upted needs to be initiated again. if a ha rdware reset is initiated during a softwa re reset operation, the hardware reset might be ignored. 12.3.1 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 131 on page 130 , table 54 on page 130 . the device must not be se lected (cs# to go high with v cc ) during power-up (t pu ), i.e. no commands may be sent to the device until the end of t pu . reset# and io3 / reset# reset function is ignored during por. if reset# or io3 / reset# is low during por and remains low through and beyond the end of t pu , cs# must remain high until t rh after reset# and io3 / reset# returns high. reset# and io3 / reset# must return high for greater than t rs before returning low to initiate a hardware reset. the io3 / reset# input functions as the reset# signal when cs# is high for more than t cs time or when quad or qpi mode is not enabled cr1v[1]=0 or cr2v[3]=0. figure 136. reset low at the end of por figure 137. reset high at the end of por figure 138. por followed by hardware reset table 58. capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#, reset#, io3 / reset#) 1 mhz ? 8 pf c out output capacitance (applies to all i/o) 1 mhz ? 8 pf vcc reset# cs# if reset# is low at tpu end cs# must be high at tpu end tpu trh vcc reset# cs# if reset# is high at tpu end cs# may stay high or go low at tpu end tpu tpu vcc reset# cs# trs tpu tpu document number: 002-00124 rev. *f page 137 of 158 s25fl256l/S25FL128L 12.3.2 reset # and io3 / reset# input initiated hardware (warm) reset the reset# and io3 / reset# inputs can function as the reset# signal. both inputs can initiate the reset operation under conditions. the reset# input initiates the reset operation when transitions from v ih to v il for > t rp , the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is performed during por. the hardware reset process requires a period of t rph to complete. the reset# input is available only on the soic 16 lead and bga ball packages. the io3 / reset# input initiates the reset operation under the following when cs# is high for more than t cs time or when quad or qpi mode is not enabled cr1v[1]=0 or cr2v[3]=0. t he io3 / reset# input has an internal pull-up to v cc and may be left unconnected if quad or qpi mode is not used. the t cs delay after cs# goes high gives the memo ry or host system time to drive io3 high after its use as a quad or qpi mode i/o signal while cs# was low. the internal pull-up to v cc will then hold io3 / reset# high until the host system begins driving io3 / reset#. the io3 / reset# input is ignored while cs# remains high during t cs , to avoid an unintended reset operation. if cs# is driven low to start a new command, io3 / reset# is used as io3. when the device is not in quad or qpi mode or, when cs# is high, and io3 / reset# transitions from v ih to v il for > t rp , following t cs , the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is performed during por. the hardware reset process requires a period of t rph to complete. if the por process did not complete correctly for any reason during power-up (t pu ), reset# going low will init iate the full por process instead of th e hardware reset proce ss and will require t pu to complete the por process. the software reset command (rsten 66h followed by rst 99h) is independent of the state of reset # and io3 / reset#. if reset# and io3 / reset# is high or unconnect ed, and the software reset instructions ar e issued, the device will perform softwar e reset. additional notes: ? if both reset# and io3 / reset# input options are availa ble use only one reset option in your system. io3 / reset# input reset operation can be disable by setting cr2nv[7]=0 (see table 14, configuration regist er 2 non-volatile (cr2nv) on page 34 ) setting the io3_reset to only operate as io3. the re set# input can be disable by not connecting or tying the reset# input to v ih . reset# and io3 / reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. ? when io3 / reset# is driven low for at least a minimum period of time (t rp ), following t cs , the device terminates any operation in progress, makes all outputs high impedance, and ignores all read/w rite commands for the duration of t rph . the device resets the interface to standby state. ? if quad or qpi mode and the io3 / reset# feature are en abled, the host system should not drive io3 low during t cs, to avoid driver contention on io3. immediatel y following commands that transfer data to the host in quad or qpi mode, e.g. quad i/o read, the memory dr ives io3 / reset# high during t cs, to avoid an unintended reset operation. immediately following commands th at transfer data to the memory in quad mode, e.g. page progra m, the host system should drive io3 / reset# high during t cs, to avoid an unintended reset operation. ? if quad or qpi mode is not enabled, and if cs# is low at th e time io3 / reset# is assert ed low, cs# must return high during t rph before it can be asserted low again after t rh . notes: 1. reset# and io3 / reset# low is ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. if quad or qpi mode is enabled, io3 / reset# low is ignored during t cs 3. sum of t rp and t rh must be equal to or greater than t rph. table 59. hardware reset parameters parameter description limit time unit t rs reset setup - prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 100 s t rp reset# pulse width min 200 ns t rh reset hold - reset# high before cs# low min 150 ns document number: 002-00124 rev. *f page 138 of 158 s25fl256l/S25FL128L figure 139. hardware reset using reset# input figure 140. hardware reset wh en quad or qpi mode is not enabled and io3 / reset # is enabled figure 141. hardware reset when quad or qpi mode and io3 / reset# are enabled reset# cs# any prior reset trs trp trh trh trph trph io3_reset# cs# any prior reset trs trp trh trh trph trph io3_reset# cs# reset pulse prior access using io3 for data trh tcs tdis trp trph document number: 002-00124 rev. *f page 139 of 158 s25fl256l/S25FL128L 12.4 sdr ac characteristics notes: 1. t crt , t clch clock rise and fall slew rate for fast clock (108 mhz) min is 1.5 v/ns and for slow clock (50 mhz) min is 1.0 v/ns. 2. full v cc range and cl=30 pf. 3. full v cc range and cl=15 pf. 4. output hi-z is defined as the point where data is no longer driven. 5. t dis require additional time when the reset feature and quad mode are enabled (cr2v[7]=1 and cr1v[1]=1). 6. only applicable as a constraint for wrr or wrar instruction when srp0 is set to a 1. table 60. sdr ac characteristics symbol parameter min max unit f sck, r sck clock frequency for read and 4read instructions dc 50 mhz f sck, c sck clock frequency for the following dual and quad commands: qor, 4qor, dior, 4dior, qior, 4qior dc 133 mhz p sck sck clock period 1/ f sck ? ? t wh , t ch clock high time 50% p sck 5% ? ns t wl , t cl clock low time 50% p sck 5% ? ns t crt , t clch clock rise time (slew rate) (1) 0.1 ? v/ns t cft , t chcl clock fall time (slew rate) (1) 0.1 ? v/ns t cs cs# high time (any read instructions) 20 ? ns cs# high time (all other non-read instructions) 50 ? ns t css cs# active setup time (re lative to sck) 3 ? ns t csh cs# active hold time (relative to sck) 5 ? ns t su data in setup time 3 ? ns t hd data in hold time 2 ? ns t v clock low to output valid ? 8 (2) 6 (3) ns t ho output hold time 1 ? ns t dis output disable time (4) output disable time (when reset feature and quad mode are both enabled) ? 8 20 (5) ns t wps wp# setup time (6) 20 ? ns t wph wp# hold time (6) 100 ? ns t dp cs# high to deep power down mode ? 3 us t res cs# high to release from deep power down mode ? 5 s t qen qio or qpi enter mode, time needed to issue next command ?1.5s t qexn qio or qpi exit mode, time needed to issue next command ?1s document number: 002-00124 rev. *f page 140 of 158 s25fl256l/S25FL128L 12.4.1 clock timing figure 142. clock timing 12.4.2 input / output timing figure 143. spi single bit input timing figure 144. spi single bit output timing v il max v ih min tch tcrt tcft tcl v cc / 2 p sck cs# sck si_io0 so msb in lsb in tcss tcsh tcs tsu thd cs# sck si_io0 so_io1 msb out lsb out tcs tho tv tdis document number: 002-00124 rev. *f page 141 of 158 s25fl256l/S25FL128L figure 145. sdr mio timing figure 146. wp# input timing cs# sclk io msb in lsb in msb ou t . lsb out tcsh tcss tsu thd tho tcs tdis tv tv cs# wp# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 wrr or wrar instruction input data twps twph document number: 002-00124 rev. *f page 142 of 158 s25fl256l/S25FL128L 12.5 ddr ac characteristics notes: 1. full v cc range and cl=30 pf. 2. full v cc range and cl=15 pf. 3. not tested. 12.5.1 ddr input timing figure 147. sp i ddr input timing table 61. ddr ac characteristics 66 mhz operation symbol parameter min max unit f sck, r sck clock frequency for ddr read instruction dc 66 mhz p sck, r sck clock period for ddr read instruction 1/f sck ?ns t crt clock rise time (slew rate) 1.5 ? v/ns t cft clock fall time (slew rate) 1.5 ? v/ns t wh , t ch clock high time 50% p sck -5% ? ns t wl , t cl clock low time 50% p sck -5% ? ns t cs cs# high time (read instructions) cs# high time (read instructions when reset feature is enabled) 20 50 ?ns t css cs# active setup time (re lative to sck) 3 ? ns t su io in setup time 3 ? ns t hd io in hold time 2 ? ns t v clock low to output valid ? 8 (1) 6 (2) ns t ho output hold time 1 ? ns t dis output disable time output disable time (when reset feature is enabled) ? 8 20 ns t o_skew first io to last io data valid time ? 600 (3) ps cs# sck io's inst. msb msb in lsb in tcss tcs tsu tsu thd thd document number: 002-00124 rev. *f page 143 of 158 s25fl256l/S25FL128L 12.5.2 ddr output timing figure 148. spi ddr output timing figure 149. spi ddr data valid window notes: 1. t clh is the shorter duration of t cl or t ch . 2. t o_skew is the maximum difference (delta) between the minimum and maximum t v (output valid) across all io signals. 3. t ott is the maximum output transition time from one va lid data value to the next valid data value on each io. 4. t ott is dependent on system level considerations including: a. memory device output impedance (drive strength). b. system level parasitics on the ios (primarily bus capacitance). c. host memory controller input v ih and v il levels at which 0 to 1 and 1 to 0 transitions are recognized. d. as an example, assuming that the above considerations result an memory output slew rate of 2 v/ns and a 3 v transition (from 1 to 0 or 0 to 1) is required by the host, the t ott would be: t ott = 3 v/(2 v/ns) = 1.5 ns. e. t ott is not a specification tested by cypress, it is system dependent and must be derived by the sys tem designer based on the above considerations. cs# sck io's msb lsb tcs tv tv tdis tho sck io slow io fast io_valid slow d1 s . slow d2 fast d1 fast d2 d1 d2 t v t io_skew t dv t cl t ch t ott p sck t ho t v _min t v document number: 002-00124 rev. *f page 144 of 158 s25fl256l/S25FL128L 12.5.3 ddr minimum data valid window the minimum data valid window (t dv ) can be calculated as follows: as an example, assuming: 66 mhz clock frequency = 15 ns clock per iod with ddr operations are specified to have a duty cycle of 45% or higher. ? t clh = 0.45*psck = 0.45 ? 15 ns = 6.75 ns ? t o_skew = 600 ps ? t ott = 1.5 ns ? t dv = t clh - t o_skew - t ott ?t dv = 6.75 ns - 600 ps - 1.5 ns = 4.65 ns ? t v _min = t ho + t o_skew + t ott ?t v _min = 1.0 ns + 600 ps + 1.5 ns = 3.1 ns 12.6 embedded algorithm performance tables notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0 v; 10,000 cycles; checkerboard data pattern. 2. the programming time for any otp programming command is the same as t pp . this includes irpp 2fh, passp e8h and pdlrnv 43h. 3. for multiple bytes after firs byte within a page t bpn = t bp1 + t bp2 * n (typical and t bpn = t bp1 = t bp2 * n (max), where n = number of bytes programmed. table 62. dual quad program and erase performance symbol parameter min typ (1) max unit t w non-volatile register write time ? 145 750 ms t pp page programming (256 bytes) ? 300 1,200 s t bp1 byte programming (first byte) (3) ?5060s t bp2 additional byte programming (after first byte) (3) ?620s t se sector erase time (4kb physical sectors) ? 50 250 ms t hbe half block erase time (32kb physical sectors) ? 190 363 ms t be block erase time (64kb physical sectors) ? 270 725 ms t ce chip erase time (S25FL128L) ? 70 180 sec t ce chip erase time (s25fl256l) ? 140 360 sec table 63. program or erase suspend ac parameters parameter typical max unit comments suspend latency (t sl ) ? 40 s the time from suspend command until the wip bit is 0. resume to next suspend (t rns ) 100 ? s is the time needed to issue the next suspend command. document number: 002-00124 rev. *f page 145 of 158 s25fl256l/S25FL128L 13. ordering information 13.1 ordering part number the ordering part number is formed by a valid combination of the following: note: 1. wson 6 x 8 mm is for s25fl256l only. wson 5 x 6 mm is for S25FL128L only. s25fl 256 l ag m f i 00 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 00 = soic16 footprint (300 mil) 01 = soic8 (208 mil) / 8-contact wson footprint 02 = 5 x 5 ball bga footprint 03 = 4 x 6 ball bga footprint temperature range / grade i = industrial (?40 c to +85 c) v = industrial plus (?40 c to +105 c) a = automotive, aec-q100 grade 3 (?40 c to +85 c) b = automotive, aec-q100 grade 2 (?40 c to +105 c) m = automotive, aec-q100 grade 1 (?40 c to +125 c) package materials f = halogen-free, lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin soic / 8-lead soic n = 8-contact wson 6 x 8 mm / wson 5 x 6 mm (1) b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed ag= 133 mhz dp = 66 mhz ddr device technology l = 65 nm floating gate process technology density 128 = 128 mb 256 = 256 mb device family s25fl cypress memory 3.0 volt-only, spi flash memory document number: 002-00124 rev. *f page 146 of 158 s25fl256l/S25FL128L valid combinations ? standard valid combinations list configurations planne d to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. table 64. valid combinations ? standard valid combinations ? standard base ordering part number speed option package and temperature model number packing type package marking S25FL128L ag mfi, mfv 00 0, 1, 3 (base) + a + (temp) + f + (model number) ag mfi, mfv 01 0, 1, 3 (base) + a + (temp) + f + (model number) ag nfi, nfv 01 0, 1, 3 (base) + a + (temp) + f + (model number) ag bhi, bhv 02, 03 0, 3 (base) + a + (temp) + h + (model number) dp mfi, mfv 00 0, 1, 3 (base) + d + (temp) + f + (model number) dp mfi, mfv 01 0, 1, 3 (base) + d + (temp) + f + (model number) dp nfi, nfv 01 0, 1, 3 (base) + d + (temp) + f + (model number) dp bhi, bhv 02, 03 0, 3 (base) + d + (temp) + h + (model number) s25fl256l ag mfi, mfv 00 0, 1, 3 (base) + a + (temp) + f + (model number) ag nfi, nfv 01 0, 1, 3 (base) + a + (temp) + f + (model number) ag bhi, bhv 02, 03 0, 3 (base) + a + (temp) + h + (model number) dp mfi, mfv 00 0, 1, 3 (base) + d + (temp) + f + (model number) dp nfi, nfv 01 0, 1, 3 (base) + d + (temp) + f + (model number) dp bhi, bhv 02, 03 0, 3 (base) + d + (temp) + h + (model number) document number: 002-00124 rev. *f page 147 of 158 s25fl256l/S25FL128L valid combinations ? au tomotive grade / aec-q100 the table below lists configurations that are automotive grade / aec-q100 qualified and are planned to be available in volume. the table will be updated as new combinations are released. consult your local sales representative to confirm availability of spec ific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that require iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are not manu factured or documented in full compliance with iso/ts- 16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. table 65. valid combinations ? automotive grade / aec-q100 valid combinations ? automotive grade / aec-q100 base ordering part number speed option package and temperature model number packing type package marking S25FL128L ag mfa, mfb, mfm 00 0, 1, 3 (base) + a + (temp) + f + (model number) ag mfa, mfb, mfm 01 0, 1, 3 (base) + a + (temp) + f + (model number) ag nfa, nfb, nfm 01 0, 1, 3 (base) + a + (temp) + f + (model number) ag bha, bhb, bhm 02, 03 0, 3 (base) + a + (temp) + h + (model number) dp mfa, mfb, mfm 00 0, 1, 3 (base) + d + (temp) + f + (model number) dp mfa, mfb, mfm 01 0, 1, 3 (base) + d + (temp) + f + (model number) dp nfa, nfb, nfm 01 0, 1, 3 (base) + d + (temp) + f + (model number) dp bha, bhb, bhm 02, 03 0, 3 (base) + d + (temp) + h + (model number) s25fl256l ag mfa, mfb, mfm 00 0, 1, 3 (base) + a + (temp) + f + (model number) ag nfa, nfb, nfm 01 0, 1, 3 (base) + a + (temp) + f + (model number) ag bha, bhb, bhm 02, 03 0, 3 (base) + a + (temp) + h + (model number) dp mfa, mfb, mfm 00 0, 1, 3 (base) + d + (temp) + f + (model number) dp nfa, nfb, nfm 01 0, 1, 3 (base) + d + (temp) + f + (model number) dp bha, bhb, bhm 02, 03 0, 3 (base) + d + (temp) + h + (model number) document number: 002-00124 rev. *f page 148 of 158 s25fl256l/S25FL128L 14. physical diagrams 14.1 soic 16-lead, 300- mil body width (so3016) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 0.33 c 0.25 m d ca-b 0.20 c a-b 0.10 c 0.10 c 0.10 c d 2x 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the h 0 d l2 n e a1 b c e e1 a 0.75 10.30 bsc 1.27 bsc 0.30 10.30 bsc 0.33 0 0.25 16 0.20 7.50 bsc 0.10 0.31 8 0.51 2.65 2.35 a2 2.05 2.55 b1 0.27 0.48 0.30 0.20 c1 l1 0.40 l 1.27 1.40 ref 0.25 bsc 0 5 15 0 0 1 2 - dimensions symbol min. nom. max. - - - - - - - - - - - - mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. so3016 kota besy 24-oct-16 24-oct-16 *a 002-15547 package outline, 16 lead soic 12 to fit 10.30x7.50x2.65 mm so3016/sl3016/ss3016 sl3016 ss3016 document number: 002-00124 rev. *f page 149 of 158 s25fl256l/S25FL128L 14.2 soic 8-lead, 208 m il body width (soc008) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 5.28 bsc d 0.51 2 0 1 0 0 n l1 l2 e1 l e e 15 0 5 8 0.76 5.28 bsc 8.00 bsc 1.36 ref 0.25 bsc 8 1.27 bsc 1.70 1.75 0.05 0.33 0.36 0.15 0.19 c1 c b1 b a2 a1 a 1.90 2.16 0.25 0.48 0.46 0.20 0.24 0-8 ref 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. dimensions symbol min. nom. max. - - - - - - - - - - kota besy 18-jul-16 18-jul-16 ** 12 to fit soc008 002-15548 package outline, 8 lead soic 5.28x5.28x2.16 mm soc008 document number: 002-00124 rev. *f page 150 of 158 s25fl256l/S25FL128L 14.3 wson 8-contact 5 x 6 mm leadless (wnd008) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date a maximum 0.15mm pull back (l1) may be present. bilateral coplanarity zone applies to the exposed heat sink pin #1 id on top will be located within the indicated zone. maximum allowable burr is 0. 076mm in all directions. dimension "b" applies to metallized terminal and is measured n is the total number of terminals. all dimensions are in millimeters. dimensioning and tolerancing conforms to asme y14.5m-1994. notes: max. package warpage is 0.05mm. 8 7. 6. 5 2. 4 3. 1. 9 10 the optional radius on the other end of the terminal, the dimension "b" should not be measured in that radius area. nd refers to the number of terminals on d side. 8 4 1.27 bsc. 0.40 6.00 bsc 5.00 bsc 4.00 3.40 0.20 min. 0.75 0.02 0.60 a1 k a e2 d e d2 b l nd n e 0.00 3.30 0.70 3.90 0.35 0.55 3.50 0.05 0.80 4.10 0.45 0.65 a3 0.20 ref dimensions symbol min. nom. max. between 0.15 and 0.30mm from terminal tip. if the terminal has slug as well as the terminals. kota lksu 13-feb-17 13-feb-17 ** 12 to fit wnd008 002-18755 package outline, 8 lead dfn 5.0x6.0x0.8 mm wnd008 4.0x3.4 mm epad (sawn) document number: 002-00124 rev. *f page 151 of 158 s25fl256l/S25FL128L 14.4 wson 8-contact 6 x 8 mm leadless (wng008) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date a maximum 0.15mm p ull back (l1) may be present. bilateral coplanarity zone applies to the exposed heat sink pin #1 id on top will be located within the indicated zone. maximum allowable burr is 0. 076mm in all directions. dimension "b" applies to metallized terminal and is measured n is the total number of terminals. all dimensions are in millimeters. dimensioning and tolerancing conforms to asme y14.5m-1994. notes: max. package warpage is 0.05mm. 8 7. 6. 5 2. 4 3. 1. 9 10 the optional radius on the other end of the terminal, the dimension "b" should not be measured in that radius area. nd refers to the number of terminals on d side. 8 4 1.27 bsc. 0.40 8.00 bsc 6.00 bsc 4.80 4.65 0.20 min. 0.75 0.02 0.50 a1 k a e2 d e d2 b l nd n e 0.00 4.55 0.70 4.70 0.35 0.45 4.75 0.05 0.80 4.90 0.45 0.55 a3 0.20 ref dimensions symbol min. nom. max. between 0.15 and 0.30mm from terminal tip. if the terminal has slug as well as the terminals. kota lksu 17-feb-17 17-feb-17 ** 12 to fit wng008 002-18827 package outline, 8 lead dfn 6.0x8.0x0.8 mm wng008 4.80x4.65 mm epad (sawn) document number: 002-00124 rev. *f page 152 of 158 s25fl256l/S25FL128L 14.5 ball grid array 24-ball 6 x 8 mm (fab024) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size md x me. when there is an even number of solder balls in the outer row, "sd" = ed/2 and when there is an odd number of solder balls in the outer row, "sd" or "se" = 0. position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define the symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 2. 1. notes: sd b ed ee me n 0.35 0.00 bsc 1.00 bsc 1.00 bsc 0.40 24 5 0.45 d1 md e1 e d a a1 0.20 - 4.00 bsc 4.00 bsc 5 6.00 bsc 8.00 bsc - - 1.20 - se 0.00 bsc dimensions symbol min. nom. max. "se" = ee/2. fab024 kota besy 18-jul-16 18-jul-16 ** 002-15534 package outline, 24 ball fbga 12 to fit 8.0x6.0x1.2 mm fab024 document number: 002-00124 rev. *f page 153 of 158 s25fl256l/S25FL128L 14.6 ball grid array 24-ball 6 x 8 mm (fac024) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size md x me. when there is an even number of solder balls in the outer row, "sd" = ed/2 and when there is an odd number of solder balls in the outer row, "sd" or "se" = 0. position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define the symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 2. 1. notes: sd b ed ee me n 0.35 0.50 bsc 1.00 bsc 1.00 bsc 0.40 24 4 0.45 d1 md e1 e d a a1 0.25 - 5.00 bsc 3.00 bsc 6 6.00 bsc 8.00 bsc - - 1.20 - se 0.50 bsc dimensions symbol min. nom. max. "se" = ee/2. fac024 kota besy 18-jul-16 18-jul-16 ** 002-15535 package outline, 24 ball fbga 12 to fit 8.0x6.0x1.2 mm fac024 document number: 002-00124 rev. *f page 154 of 158 s25fl256l/S25FL128L 15. other resources 15.1 glossary bcd binary coded decimal. a value in which each 4 bit nibble represents a decimal numeral. command all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes called an operatio n code or opcode) and any required address, mode bits, latency cycles, or data. ddp dual die package = two die stacked within the same package to increase the memory capacity of a single package. often also referred to as a multi-chip package (mcp). ddr double data rate = when input and output are latched on every edge of sck. flash the name for a type of electrical erase programmable r ead only memory (eeprom) that erases large blocks of memory bits in parallel, making the erase operation much faster than early eeprom. high a signal voltage level v ih or a logic level representing a binary one (?1?). instruction the 8 bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). the instruction is always the first 8 bits transf erred from host system to the memory in any command. low a signal voltage level ? v il or a logic level representing a binary zero (?0?). lsb least significant bit = generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. msb most significant bit = generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. n/a not applicable. a value is not relevant to situation described. non-volatile no power is needed to maintain data stored in the memory. opn ordering part number = the alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device. qpi quad peripheral interface page 256 byte length and aligned group of data. pcb printed circuit board register bit references in the format: register_name[bit_number] or register_name[bit_range_msb: bit_range_lsb] sector erase unit size; depending on device model and sector location this may be 4kbytes, 32kbytes or 64kbytes sdr single data rate = when input is latched on the rising edge and output on the falling edge of sck. write an operation that changes data within volatile or non-vo latile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data. document number: 002-00124 rev. *f page 155 of 158 s25fl256l/S25FL128L 15.2 link to cypress flash roadmap www.cypress.com/product-roadmaps /cypress-flash-memory-roadmap 15.3 link to software www.cypress.com/software-and-d rivers-cypress-flash-memory 15.4 link to application notes www.cypress.com/appnotes document number: 002-00124 rev. *f page 156 of 158 s25fl256l/S25FL128L 13. document history document title: s25fl256l/S25FL128L, 256mbit (32m byte)/128mbit (16mbyte), 3.0 v fl-l flash memory document number: 002-00124 rev. ecn no. orig. of change submission date description of change ** 4905743 bwha 09/18/2015 initial release. *a 5147318 bwha 02/22/2016 dc characteristics ? industr ial, industrial plus and extended tables: changed i sb max value sdr ac characteristics tabl e: changed min values for t ch and t cl embedded algorithm performance tables: changed value for t pp max registers: added sentences; when volati le register bits are written, only the volatile version of the register has the appropriate bits updated. when either a non-volatile or vola tile register is read, the volatile version of the register is delivered. basic spi flash parameter, jedec sfdp rev b: changed 3dh data from 60h to 50h *b 5322980 bwha 06/25/2016 restructured datasheet. added S25FL128L related information in all instances across the document. updated data integrity : updated erase endurance : updated table 44 . updated data retention : updated table 45 . updated electrical specifications : added thermal resistance . updated other resources : added link to cypress flash roadmap . *c 5449210 arvr 09/26/2016 changed status from advance to final. updated features : added automotive grade related information. updated data integrity : updated data retention : updated table 45 . updated electrical specifications : updated thermal resistance : updated table 53 . updated operating ranges : updated temperature ranges : added automotive grade related information. updated ordering information : updated ordering part number : updated details corresponding to ?01? under ?model number (additional ordering options)?. added automotive grade related information. updated valid combinations ? standard . added valid combinations ? automotive grade / aec-q100 . updated physical diagrams : wson 8-contact 6 x 8 mm leadless (wnh008). added wson 8-contact 6 x 8 mm leadless (wng008) . *d 5548451 arvr 01/11/2017 updated sales information and copyright. updated links in other resources . document number: 002-00124 rev. *f page 157 of 158 s25fl256l/S25FL128L *e 5677892 ecao 05/15/2017 changed vdd to vcc. added table 36, s25fl256l (256mb) lower array lega cy block protection (tbprot = 1, cmp = 0) on page 52 updated sfdp parameter address byte 02h, bit 22 description from ?dor? to ?qor? in table 48, basic spi flash parameter, jedec sfdp rev b on page 121 updated t se value in table 62, dual quad program and erase performance on page 144 updated package material ?f? option to ?f = halogen-free, lead (pb)-free? in section 13.1, ordering part number on page 145 updated figure 14.3, wson 8-contact 5 x 6 mm leadless (wnd008) on page 150 updated figure 14.4, wson 8-contact 6 x 8 mm leadless (wng008) on page 151 updated valid combinations ? standard for S25FL128L. added valid combinations ? automotive grade / aec-q100 for S25FL128L. updated package diagram for soic 16-lead, 300-mil body width (so3016) (spec 002-15547 rev. ** to *a). updated cypress logo, sales page, and copyright information. *f 5846473 bwha 08/07/2017 updated features : removed ?s25fl256l?. updated table 52 : corrected latchup max spec. updated ordering part number : removed fl128l is not in production. updated table 64 and table 65 : added soic 16 package for the fl128l. document title: s25fl256l/S25FL128L, 256mbit (32m byte)/128mbit (16mbyte), 3.0 v fl-l flash memory document number: 002-00124 rev. ecn no. orig. of change submission date description of change document number: 002-00124 rev. *f re vised august 07, 2017 page 158 of 158 ? cypress semiconductor corporation, 2015-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors ), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, incl uding, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical co mponents in systems designed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or register ed trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. s25fl256l/S25FL128L sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support |
Price & Availability of S25FL128L
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |